Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2001-12-18
2003-03-25
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S207000, C365S208000
Reexamination Certificate
active
06538944
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to an improved semiconductor memory device which can drive sense amplifiers according to variations in operating conditions, by using a word line enable sensing block for outputting a sense amplifier driver control signal at an enable time point of a word line.
2. Description of the Background Art
FIG. 1
is a circuit diagram illustrating a conventional semiconductor memory device.
The conventional semiconductor memory device includes: a memory cell array
2
having a plurality of memory cells
1
; a sense amplifier driver control circuit
3
; a sense amplifier driver
4
; and a sense amplifier array
6
having a plurality of sense amplifiers
5
.
The memory cell array
2
includes the plurality of memory cells
1
having an array structure, each memory cell being aligned in cross points of word lines and bit lines. Each memory cell
1
includes a cell plate voltage VCP and a cell transistor TRC for transferring data stored in a storage capacitor CS to the bit.
The sense amplifier block
6
includes the plurality of sense amplifiers
5
for receiving data from the bit lines, and amplifying the received data.
The operation of the conventional semiconductor memory device will now be explained.
When a row address strobe signal RAS is generated and one of the word lines of the memory cell array
2
is enabled in a high level, the cell transistors TRC of the memory cells
1
connected to the enabled word line are turned on, thereby charge-distributing the data stored in the storage capacitor CS to the bit lines. As is known in the art, the row address strobe signal is an outside control signal for controlling the enable time of the word lines.
On the other hand, the sense amplifier driver control circuit
3
outputs a sense amplifier driver operation control signal CON after a predetermined time from generation of the row address strobe signal RAS according to a delay timing defined in design. And, the sense amplifier driver
4
receives the sense amplifier driver operation control signal CON and outputs sense amplifier enable signals RTO and /S for enabling the sense amplifiers
5
.
The sense amplifier enable signals RTO and /S from the sense amplifier driver
4
enable the sense amplifiers
5
, and the enabled sense amplifiers
5
amplify the data from the corresponding bit lines.
Now, a time interval between generation of the row address strobe signal RAS and completion of the enable operation of the word line is varied according to various conditions of the memory device such as an operation voltage, process variation and operation temperature of the memory device, and a size and number of the memory cell blocks. Therefore, a variation width of the word line enable time must be considered to decide the enable timing of the sense amplifiers
5
.
However, when the conventional semiconductor memory device controls the enable timing of the sense amplifiers
5
, the sense amplifier driver control circuit
3
outputs the sense amplifier driver operation control signal CON after a predetermined time from generation of the row address strobe signal RAS to drive the sense amplifier driver
4
. The delay time between generation of the row address strobe signal RAS and generation of the sense amplifier driver operation control signal CON is decided by a test in design.
Accordingly, the sense amplifier driver control circuit
3
is designed to output the sense amplifier driver operation control signal CON pursuant to the latest enable time of the word line in consideration of variations of the word line enable time.
When the semiconductor memory device is operated according to the latest enable completion time, an operation time is unnecessarily increased in every operation. It is thus difficult to perform a high speed operation.
In an embedded memory logic (EML) where a memory cell and a logic are integrated in one chip, operation conditions and a number and size of the memory cell arrays are varied according to uses of the logic. Here, the sense amplifier driver control circuits should have been designed to take into account all variations of the operation conditions. As a result, it is difficult to apply the conventional semiconductor memory device to the EML.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to improve an operation speed of a semiconductor memory device, by reflecting variations of a word line enable timing due to variations of operation conditions after design, such as an operation voltage, process and operation temperatures, to driving of sense.
Another object of the present invention is to simplify an EML design by automatically considering variations of operation conditions in accordance with uses of a logic, and variations of a word line enable timing in accordance with a number and size of memory cell blocks.
In order to achieve the above-described objects of the invention, there is provided a semiconductor memory device including: at least one memory block having a memory cell array composed of a plurality of memory cells each aligned in cross point of word line and bit line, and a sense amplifier array composed of a plurality of sense amplifiers for amplifying data from the plurality of memory cells; a word line sensing means for sensing an enable state of the word lines and transmitting a predetermined voltage to a sense amplifier driver; and the sense amplifier driver for driving the sense amplifiers of the memory block according to the predetermined voltage from the word line sensing means.
REFERENCES:
patent: 5291447 (1994-03-01), Komada et al.
patent: 5724293 (1998-03-01), Tomishima et al.
patent: 5946253 (1999-08-01), Fujiwara
patent: 6041004 (2000-03-01), Haga
patent: 6052324 (2000-08-01), Tobita
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Phan Trong
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