Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-02-08
2001-12-04
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S230060, C365S189090, C714S718000, C714S720000
Reexamination Certificate
active
06327198
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly to a semiconductor memory device having a function of performing a burn-in test in a molded state.
2. Description of the Background Art
Conventionally, a burn-in test has been used for testing a memory device. In the burn-in test, a stress is applied to the device to determine its reliability.
As a storage capacity of the memory device increases, the time required for the burn-in test to apply stresses to word lines also increases. For example, while a 64-M SDRAM (a Synchronous Dynamic Random Access Memory) has 4096 word lines in total, a 256-M SDRAM has as many as 8192 word lines.
In the conventional test method, a stress has been applied to one word line at a time. However, to apply the stress to the 256-M SDRAM which is equal to the stress applied to 64-M SDRAM, twice as much burn-in time is required.
In addition, under conventional semiconductor memory device is not provided with a function of investigating the cause of malfunction.
Therefore, it is required that the test is efficiently and correctly performed in a reduced amount of time. To clearly investigate the device, a detailed test program must efficiently be performed.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor memory device capable of effectively and correctly performing a burn-in test.
According to one aspect of the present invention, the semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array having a plurality of word lines arranged correspondingly to rows of the plurality of memory cells and a plurality of bit lines arranged correspondingly to columns of the plurality of memory cells; a test mode setting circuit serially setting a plurality of test modes in accordance with an external signal; and a memory control circuit writing a checker pattern to the memory cell array in accordance with an output from the test mode setting circuit. The memory control circuit includes; a row control circuit bringing even-numbered word lines/odd-numbered word lines of the plurality of word lines in a selection
on-selection state; and a column control circuit supplying a prescribed voltage for the plurality of bit lines in accordance with corresponding one of the plurality of test modes.
Preferably, the memory control circuit serially performs selection control for the even-numbered word lines or odd-numbered word lines and voltage control for the plurality of bit lines for writing data of different potentials for the memory cells respectively corresponding to the even-numbered word lines and odd-numbered word lines.
Preferably, the column control circuit includes a circuit determining the voltage of the plurality of bit lines as an internal power supply voltage higher than an equalization voltage or a ground voltage lower than the equalization voltage in a normal operation mode in response to the corresponding one of the plurality of test modes.
Preferably, each of the plurality of memory cells includes a memory cell capacitor having a cell plate and a storage node, and a memory cell transistor. The column control circuit further includes a circuit setting a voltage of the cell plate to the external power supply voltage or ground voltage in response to the corresponding one of the plurality of test modes.
Preferably, each of the plurality of memory cells includes a memory cell capacitor and a memory cell transistor. The column control circuit further includes a circuit setting a back gate voltage of the memory cell transistor to the ground voltage in response to the corresponding one of the plurality of test modes.
Therefore, in the semiconductor memory device according to one aspect of the present invention, the plurality of test modes are serially set in accordance with the external signal and the selection control for the word lines and the voltage control for the bit lines are performed in accordance with the test mode, so that the check pattern can readily be written.
At the time, the even-numbered and the odd-numbered word lines are brought into the selection
on-selection state. The voltage of the bit line is set higher (the internal power supply voltage) than the equalization voltage or lower (the ground voltage) than the equalization voltage in the normal operation mode. Thus, data written to the memory cells respectively corresponding to the even-numbered and odd-numbered word lines have different values. As a result, a leakage for the memory cell can readily be detected.
Particularly, a cell plate voltage of the memory cell capacitor is set higher (the external power supply voltage) or lower (the ground voltage) than the voltage in the normal operation mode in accordance with the test mode, so that the stress applied to the memory cell is acceleratingly increased.
Particularly, the back gate voltage is set to the ground voltage in accordance with the test mode. Thus, the stress is not undesirably applied to a PN junction of the memory cell.
According to another aspect of the present invention, the semiconductor memory device includes: a plurality of memory cells each having a memory cell capacitor with a storage node and a cell plate and a memory cell transistor; a test mode setting circuit setting a test mode in accordance with an external signal; and a voltage generating circuit generating a voltage supplied for the cell plate. The voltage generating circuit sets the voltage for the cell plate such that a stress is applied to the memory cell capacitor in accordance with an output from the test mode setting circuit.
Preferably, the voltage generating circuit sets the voltage for the cell plate to the external power supply voltage or the ground voltage in accordance with the output from the test mode setting circuit.
Therefore, in the semiconductor memory device according to another aspect of the present invention, the voltage for the cell plate of the memory cell capacitor is set higher (the external power supply voltage) or lower (the ground voltage) than the voltage in the normal operation mode in accordance with the test mode. Thus, the stress applied to the memory cell acceleratingly increases.
According to still another aspect of the present invention, the semiconductor memory device includes: a memory cell array having a plurality of memory cells each having a memory cell capacitor and a memory cell transistor; a test mode setting circuit setting a test mode in accordance with an external signal; a circuit writing a checker pattern to the memory cell array in accordance with a test mode; and a voltage generating circuit setting a back gate voltage of the memory cell transistor in accordance with the test mode.
Preferably, the voltage generating circuit sets the back gate voltage to the ground voltage in accordance with the test mode.
In the semiconductor memory device according to still another aspect of the present invention, the back gate voltage is set to the ground voltage in accordance with the test mode. Thus, the stress is not undesirably applied to a PN junction of the memory cell.
Another object of the present invention is to provide a semiconductor memory device which facilitates analysis of a test result.
According to still another aspect of the present invention, the semiconductor memory device includes: an internal circuit having a memory cell array; a test mode setting circuit serially setting a plurality of test modes in accordance with an external signal; a circuit writing a checker pattern to the memory cell array in accordance with an output from the test mode setting circuit; and a voltage generating circuit including a generator generating an internal voltage supplied for an internal circuit. The voltage generating circuit stops an operation of the generator in accordance with the corresponding one of the plurality of test modes.
Preferably, the voltage generating circuit further includes a fixing circuit setting the internal voltage to a fix
Asakura Mikio
Kato Tetsuo
Miyamoto Takayuki
Tanizaki Tetsushi
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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