Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-08-29
2006-08-29
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130, C714S006130, C714S006130, C714S710000, C714S711000, C365S200000, C365S201000
Reexamination Certificate
active
07100090
ABSTRACT:
A semiconductor memory device includes memory cells, redundant cells, a redundancy repair control circuit and a test mode control circuit. Each of the memory cells is assigned a unique address to be accessed by a corresponding address. The redundant cells are replaceable with the memory cells. The redundancy repair control circuit replaces predetermined memory cells among the memory cells with the redundant cells. The test mode control circuit invalidates an operation of the redundancy repair control circuit and assigns an additional unique address to the redundant cells so that all of the memory cells and the redundant cells are accessible during a test mode.
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Beausoliel Robert
Oki Electric Industry Co. Ltd.
Puente Emerson
VolentineFrancos&Whitt PLLC
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