Semiconductor memory device having a test cell array

Details Semiconductor memory device having a test cell array Semiconductor memory device having a test cell array

1988-09-08

1990-10-30

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Testing

365210, 365104, G11C 700, G11C 2900

Patent

active

049673947

ABSTRACT:
A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line. In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line in response to the same address signal.

REFERENCES:
patent: 4423492 (1983-12-01), Yoshida
patent: 4719599 (1988-01-01), Natsui et al.
patent: 4819212 (1989-04-01), Nakai et al.

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