Static information storage and retrieval – Read/write circuit – Testing
Patent
1988-03-22
1989-05-23
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Testing
365200, G11C 700, G11C 2900
Patent
active
048336521
ABSTRACT:
A defect detection circuit for detecting a defect of a memory cell, a counter for counting defects detected by the defect detect circuit, and a remediableness determination unit for determining whether a count of the counter allows remedy by a redundancy circuit, are provided in a tester for a semiconductor memory or on a memory chip having a redundancy circuit. When the count of the counter is the same as or smaller than the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory is determined to be "remediable." Otherwise, the memory is determined to be "unremediable." When the count of the counter exceeds the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory test is interrupted.
REFERENCES:
patent: 3940740 (1976-02-01), Coontz
patent: 3962687 (1976-06-01), Suzumura et al.
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4587638 (1986-05-01), Isobe et al.
IBM Technical Disclosure Bulletin--vol. 12, No. 6, Nov. 1969, p. 895.
Kokkonen et al., "Redundancy Techniques for Fast Static RAMs," IEEE International Solid-State Circuits Conference, ISSCC Digest of Technical Papers, pp. 80-81, Feb. 18, 1981.
Isobe Mitsuo
Kimura Tohru
Kabushiki Kaisha Toshiba
Moffitt James W.
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