Static information storage and retrieval – Powering
Reexamination Certificate
2001-08-09
2002-11-26
Elms, Richard (Department: 2824)
Static information storage and retrieval
Powering
C365S201000, C365S205000, C365S207000, C365S208000, C365S189110
Reexamination Certificate
active
06487137
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a testing method thereof, and more particularly, to a semiconductor memory device and a testing method thereof which device is tested by using a high voltage.
2. Description of the Related Art
In developing a semiconductor memory device, reducing a circuit scale has always been a concern, and thus conventional technologies have devised a semiconductor memory device having a plurality of memory cell arrays sharing a sense amplifier. The sense amplifier is generally referred to as a shared sense amplifier.
In the semiconductor memory device having the above-mentioned structure, two memory cell arrays, for example, share a sense amplifier. A gate, referred to as a bit-line transfer (BT) gate, is provided between each of the memory cell arrays and the sense amplifier. The opening and closing of each of the BT gates is controlled according to which of the memory cell arrays is targeted in reading data so that data is read selectively from either of the memory cell arrays into the sense amplifier.
Conventionally, the above-mentioned BT gates are controlled by a method referred to as “VPP driving method via VDD”. In the “VPP driving method via VDD”, the electric potentials of BT gate drive lines regulating the opening and closing of the BT gates are at the level of a power-source voltage VDD in a standby state, and then in reading or writing data, the level is driven to the level of a boosted voltage VPP or a ground voltage VSS. This method is effective in reducing an amount of electric power being consumed compared to a method of driving the BT gates continuously by the boosted voltage VPP.
However, in a wafer-level burn-in (WLBI) test, when applying a voltage of, for example, 4V to a bit line, a voltage higher than the 4V by a threshold voltage of transistors composing the BT gate has to be applied to gates of the transistors. Raising the level of the above-mentioned power-source voltage VDD to a level higher than the 4V imposes unnecessary stress on the sense amplifier supplied with the power-source voltage VDD and controlling circuits thereof, more specifically, transistors and other devices included in these circuits, the transistors and other devices having a short-length gate and driven by the internal power-source voltage. Hence, there is a problem that a WLBI test cannot be sufficiently performed.
It is noted that the “WLBI test” here means a test investigating stresses such as a leak between adjacent bit lines, or between opposing memory cells connected to a bit line leading to a sense amplifier.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved and useful semiconductor memory device and a testing method thereof in which device and method the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a semiconductor memory device which device can be tested by using a high voltage with ease, and a testing method thereof which method can test a semiconductor memory device by using a high voltage with ease.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a semiconductor memory device comprising:
at least two memory cell arrays;
a sense amplifier shared by the memory cell arrays;
at least two transfer gates connected respectively between each of the memory cell arrays and the sense amplifier;
a first voltage supplier supplying a first voltage to the transfer gates; and
a second voltage supplier supplying a second voltage to the transfer gates, the second voltage being higher than the first voltage.
The present invention can prevent unnecessary stress from imposing on unintended circuits of the semiconductor memory device.
Additionally, the semiconductor memory device according to the present invention may have a normal-operation mode and a test mode testing a quality of the memory cell arrays, wherein the second voltage supplier may be activated only in the test mode.
According to the present invention, a test testing a quality of the memory cell arrays can be easily performed.
Additionally, in the semiconductor memory device according to the present invention, the first voltage supplier may supply the transfer gates with the first voltage, in a first state in the normal-operation mode, and may supply at least one of the transfer gates with one of voltages opening and closing the transfer gate, in a second state in the normal-operation mode.
According to the present invention, reading and writing data from/to the memory cell arrays can be performed easily.
Additionally, in the semiconductor memory device according to the present invention, the second voltage supplier may supply the second voltage to all of the transfer gates.
According to the present invention, the above-mentioned test can be performed to all of the memory cell arrays at the same time.
Specifically, in the semiconductor memory device according to the present invention, each of the transfer gates may include at least one transistor having a gate supplied with the first voltage and the second voltage.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a method of testing a semiconductor memory device including at least two memory cell arrays, a sense amplifier shared by the memory cell arrays, and at least two transfer gates connected respectively between each of the memory cell arrays and the sense amplifier, the method comprising the step of:
supplying the transfer gates with a higher voltage in a test than a voltage supplied in a normal operation.
The testing method according to the present invention can prevent unnecessary stress from imposing on unintended circuits of the semiconductor memory device.
Additionally, in the method according to the present invention, the semiconductor memory device may have a test mode testing a quality of the memory cell arrays, and the step of supplying may include regulating the higher voltage supplied to the transfer gates according to a signal activated by the semiconductor memory device in the test mode.
According to the present invention, a test testing a quality of the memory cell arrays can be easily performed.
Additionally, the method according to the present invention may further comprise the steps of:
supplying the transfer gates with a first voltage, in a first state in the normal operation; and
supplying at least one of the transfer gates with one of second and third voltages opening and closing the transfer gate, in a second state in the normal operation.
According to the present invention, reading and writing data from/to the memory cell arrays can be performed easily.
Additionally, in the method according to the present invention, the step of supplying may supply the higher voltage to all of the transfer gates.
According to the present invention, the above-mentioned test can be performed to all of the memory cell arrays at the same time.
Specifically, in the method according to the present invention, each of the transfer gates may include at least one transistor, and the step of supplying may supply the higher voltage to a gate of the transistor.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5394374 (1995-02-01), Ishimura et al.
patent: 5862095 (1999-01-01), Takahashi et al.
patent: 5894445 (1999-04-01), Kobayashi
patent: 6088819 (2000-07-01), Adachi et al.
patent: 6181618 (2001-01-01), Inaba et al.
Fujioka Shin-ya
Nishimura Koichi
Tsuboi Hiroyoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Elms Richard
Fujitsu Limited
Le Toan
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