Semiconductor memory device having a redundant memory

Details Semiconductor memory device having a redundant memory Semiconductor memory device having a redundant memory

1999-06-07

2000-11-07

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

061445924

ABSTRACT:
An internal address signal generation circuit generates an internal address signal necessary for accessing a memory cell array. A defective address storage circuit stores a defective address signal of the memory cell array. A first comparison circuit compares the internal address signal and defective address signal. A latch circuit latches a redundant testing address signal supplied from outside. A second comparison circuit compares the redundant testing address signal and the internal address signal. A selection circuit selects an output signal of the second comparison circuit in a redundant test mode. In response to the selected output signal, part of the memory cell array is replaced with a redundant memory cell array.

REFERENCES:
patent: 5818771 (1998-10-01), Yasu et al.
patent: 5970001 (1999-10-01), Noda et al.

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