Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-23
2003-01-21
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S297000, C365S200000, C365S222000
Reexamination Certificate
active
06509598
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor memory device, and especially to a semiconductor memory device in which a defective memory cell is replaced with a redundant memory cell array when a defective part occurs in a main memory and information on an address of a defective memory cell is generated by selectively disconnecting fuses.
BACKGROUND OF THE INVENTION
In a semiconductor memory device, it sometimes occurs that a memory cell array does not operate because it is used exceeding a margin determined at the time of designing or fabrication, or fabricated imperfectly. If there is a part which does not operate as mentioned in the above, the whole semiconductor memory device may be regarded as inferior goods.
Hitherto, a defective memory cell array is replaced with a redundant memory cell array prepared previously on the basis of information on an address of the defective memory cell which is obtained in a test performed before the semiconductor memory is packaged. When the defective memory cell array is replaced with the redundant memory array, information on the address of the defective memory cell is generated by selectively disconnecting fuses. In case that the defective memory cell array is replaced with the redundant memory cell array, the address of the defective memory cell is assigned to that of the redundant memory cell array on the basis of information on the address of the defective memory cell. Accordingly, when an address signal corresponding to the defective memory cell is inputted, the memory cell of the redundant memory cell array is selected, and the semiconductor memory device is kept to be used as an excellent article though there is a defective part therein.
FIG. 1
shows a conventional semiconductor memory device. Although a single redundant circuit is shown in
FIG. 1
, the number of the redundant circuits is the same as that of the redundant memory cell arrays in the actual semiconductor memory device.
The semiconductor memory device shown in
FIG. 1
is composed of a constant current-generating unit
1
, latches
20
A,
20
B,
20
C,
20
D,
20
E,
20
F, P-type MOS transistors
30
,
31
,
32
,
33
,
34
,
35
, fuses (Fus)
40
,
41
,
42
,
43
,
44
,
45
, transfer gates (TGs)
50
,
51
,
52
,
53
,
54
,
55
and an inverter
60
. Although a single fuse block corresponding to a single memory cell array is shown in
FIG. 1
, the plural fuse blocks are provided in accordance with the number of the memory cell arrays in the actual semiconductor memory device. Moreover, the memory cell array is omitted in FIG.
1
.
The constant current-generating unit
10
is composed of an inverter
11
for inverting a reset signal Sr, a N-type MOS transistor
12
operating in accordance with an output signal of the inverter
11
, a P-type MOS transistor
13
inserted between the N-type MOS transistor
12
and a power supply VDD, a P-type MOS transistor
14
inserted between the power supply VDD and a gate of the P-type MOS transistor
13
, and a resistor
15
connected with a source of the N-type MOS transistor
12
and the ground GND. The gate of the P-type MOS transistor
13
is connected with the drain of the N-type MOS transistor
12
.
Since structures of the latches
20
A to
20
F are the same, only the structure of the latch
20
A will be explained here, and explanations on those of the other latches will be omitted. The latch
20
A is composed of a transfer gate
21
and inverters
22
,
23
. In the transfer gate
21
, the inverter
22
is inserted between a terminal A and an output terminal of FOS, an inverter
23
is inserted between a terminal B and the output terminal of FOS, a terminal C is connected with a terminal
70
, and a terminal C bar is connected with an output terminal of the inverter
60
and a terminal C of the transfer gate
50
. The fuse information FOS is outputted from the latch
20
A. Fuse disconnection informations F
01
to F
05
for specifying addresses of defective memory cells in the main memory cell array are respectively outputted from the latches
20
B to
20
F. In the transfer gate
50
, a terminal C bar is connected with the terminal
70
, a terminal A is connected with a terminal of the fuse
40
on the side of a high potential, and a terminal B is connected with an input terminal of the inverter
23
. The fuse
40
is provided to generate the fuse information FOS for deciding whether the redundant circuit is used or not.
Gates of the P-type MOS transistors
30
to
35
are connected with an output terminal (a FC signal-output terminal) of the constant current-generating unit
10
, sources of the same are respectively connected with the power supply VDD, and drains of the same are respectively connected with the fuses
40
to
45
. The other terminals of the fuses
40
to
45
commonly connected with the ground GND.
FIG. 2
explains operations of important structural elements shown in FIG.
1
.
FIG. 3
explains an operation of the constant current-generating unit
10
. An operation of the semiconductor memory device shown in
FIG. 1
will be explained referring to
FIGS. 1
,
2
, and
3
.
In an ordinary state, the high logical level is applied to the terminal
70
. Accordingly, the low logical level is applied to the N-type MOS transistor
12
via the inverter
11
in the constant current-generating unit
10
. Then, the N-type MOS transistor
12
turns off, and the P-type MOS transistor
14
turns on. Since the P-type MOS transistor
14
turns on, a terminal
71
is precharged by the power supply VDD, and the P-type MOS transistor
13
turns off. Accordingly, the P-type MOS transistor
30
to
35
turn off, and a current flows through none of the fuses
40
to
45
, and terminal voltages of the fuses
40
to
45
which are respectively denoted by FMS, FM
1
to FM
5
are at uncertain levels.
At this time, in each of the transfer gates
50
to
55
, since the low logical level is applied to the terminal C via the inverter
60
and the high logical level is applied to the terminal C bar from the terminal
70
, each of the transfer gates
50
to
55
turns off. On the other hand, in the transfer gate
21
of each of the latches
20
A to
20
F, since the high logical level is applied to the terminal C from the terminal
70
and the low logical level is applied to the terminal C bar via the inverter
60
, the transfer gate
21
turns on.
Next, a case that a reset signal Sr is inputted to the terminal
70
when the memory is initialized will be explained. The reset signal Sr changes into the low logical level in one-shot.
Since the reset signal Sr inputted to the terminal
70
is inverted by the inverter
11
in the constant current-generating unit
10
and inputted to the gate of the N-type MOS transistor
12
, the N-type MOS transistor
12
and the P-type MOS transistor
13
turn on, and the P-type MOS transistor
14
turns off. As a result, a voltage at a certain level is impressed upon the terminal
71
as the FC signal, and the P-type MOS transistors
30
to
35
turn on simultaneously, since the fuses
40
to
45
are respectively connected with the P-type MOS transistors
30
to
35
, a fuse current flow in case that the fuse is connected and does not flow in case that the fuse is disconnected. A voltage is generated between the terminals of the fuse
40
,
41
, . . . , or
45
in case that the fuse current does not flow. That is to say, whether the fuse is disconnected or not can be discriminated on the basis of the terminal voltage of the fuse as shown in FIG.
2
.
At this time, in each of the transfer gates
50
to
55
, the reset signal Sr at the low logical level is applied to the terminal C bar, and the high logical level, which is derived by inverting the reset signal Sr by the inverter
60
, is applied to the terminal C. Accordingly, each of the transfer gates
50
to
55
turns on, and an input signal supplied to the terminal A is transmitted to the terminal B straightly. For instance, if the fuse
40
is disconnected since the terminal voltage FMS of the fuse
40
is at the high logical level
Abraham Fetsum
Katten Muchin Zavis & Rosenman
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