Semiconductor memory device having a redundancy memory cell...

Details Semiconductor memory device having a redundancy memory cell... Semiconductor memory device having a redundancy memory cell...

2009-06-24

2011-11-08

Le, Vu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060

Reexamination Certificate

active

08054704

ABSTRACT:
A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.

REFERENCES:
patent: 6597607 (2003-07-01), Koshita
patent: 2006/0098503 (2006-05-01), Jeong et al.
patent: 2007/0268761 (2007-11-01), Singh
patent: 2008/0298154 (2008-12-01), Mae
patent: 100196515 (1999-06-01), None
patent: 100735836 (2007-07-01), None
patent: 1020070069745 (2007-07-01), None
patent: 1020080016475 (2008-02-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Nov. 11, 2010.
Notice of Allowance issued from Korean Intellectual Property Office on Jun. 3, 2011.

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