Semiconductor memory device having a plurality of row address st

Details Semiconductor memory device having a plurality of row address st Semiconductor memory device having a plurality of row address st

1993-02-01

1994-08-30

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

365193, G11C 800

Patent

active

053434382

ABSTRACT:
The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory for accomplishing high speed data access by supplying a plurality of row address strobe signals to a chip. A plurality of row address strobe signals are supplied to a plurality of pins, and each row address strobe signal is sequentially supplied with an active signal during a data access operation. Therefore, data in a plurality of memory cell arrays is accessed during one access cycle time. Thus, since a large number of random data are provided, the data access time decreases and the performance of a system can be greatly improved.

REFERENCES:
patent: 4636986 (1987-01-01), Pinkham
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 4881206 (1989-11-01), Kadono
patent: 4967397 (1990-10-01), Walck
patent: 4998222 (1991-03-01), Sussman

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