Semiconductor memory device having a plurality of power voltages

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257371, G11C 700

Patent

active

059301910

ABSTRACT:
A semiconductor memory device operable under a first power voltage and a second power voltage which are different from each other. The memory device includes a substrate of a first conductivity type, a well of a second conductivity type defined in said substrate, and first and second inverter circuits defined serially with one another on the substrate and common well. The first inverter circuit includes a first transistor of a second conductivity type on the substrate and a first transistor of a first conductivity type on the well for receiving a first power voltage and generating a first inverted output voltage in response to a first input voltage applied to gates of the respective first transistors. The second inverter circuit includes a second transistor of a second conductivity type on the substrate and a second transistor of a first conductivity type on the well for receiving a second power voltage and generating a second inverted output voltage in response to a second input voltage applied to gates of the respective second transistors.

REFERENCES:
patent: 4754160 (1988-06-01), Ely
patent: 5285093 (1994-02-01), Lage et al.

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