Semiconductor memory device having a plurality of bank...

Details Semiconductor memory device having a plurality of bank... Semiconductor memory device having a plurality of bank...

1997-06-30

2001-03-27

Gossage, Glenn (Department: 2759)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S173000, C365S230030, C365S230060

Reexamination Certificate

active

06209056

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for distributing banks in a semiconductor memory device, in which individual cells are efficiently grouped into the banks, and more particularly to a bank distribution method for dividing each cell array vertically and horizontally into a plurality of banks and minimizing the length of a data bus to make a high-speed operation of the semiconductor memory device possible.
2. Description of the Prior Art
Generally, a group of cells individually accessed in a semiconductor memory device is called a bank. A very large scale integrated memory device requires a plurality of banks because the performance is enhanced by a bank-interleaved operation.
For example, a 16-Mbit (megabit) dynamic random access memory (DRAM) requires two banks, a 64-Mbit DRAM requires four banks, a 256-Mbit DRAM requires eight or sixteen banks, and a 1-Gbit (gigabit) DRAM requires thirty-two or more banks.
The distribution of banks is performed for the improvement in operation speed of a semiconductor memory device. This is due to the fact that the operation speed of the semiconductor memory device is much lower than that of a microprocessor, resulting in a degradation in the entire system performance. As a result, in order to meet high speed and high bandwidth requirements of the semiconductor memory device, a plurality of banks must be provided in the memory device. Such a conventional bank distribution method for the semiconductor memory device will hereinafter be described with reference to FIG.
1
.
FIG. 1
is a view illustrating a distributed bank configuration of a conventional semiconductor memory device. As shown in this drawing, the conventional semiconductor memory device comprises a plurality of banks (for example, four banks
0
-
3
), each of which is provided with two bank sections, or left and right bank sections, corresponding respectively to cell arrays. A column decoder is connected to each of the left and right bank sections, and a row decoder is positioned between the left and right bank sections and connected in common to them.
A data bus is provided with N (natural number) data bus lines for transferring data from the banks
0
-
3
to N input/output pads, respectively.
However, in the above-mentioned conventional semiconductor memory device, the length of the data bus is extremely long because it transfers data from all the banks
0
-
3
to the N input/output pads, resulting in a delay in data output. Such a data output delay makes a high-speed operation of the semiconductor memory device impossible.
Further, the bank implementation requires the same number of row decoders and row control signals as that of the banks, resulting in a significant increase in chip area.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for distributing banks in a semiconductor memory device, in which each cell array is vertically and horizontally divided into a plurality of banks, resulting in a significant reduction in chip area as compared with a conventional bank distribution method. This method also allows a data bus to be minimized in length because it is localized to each cell array, so that high-speed operation of a semiconductor memory device is possible.
In accordance with one aspect of the present invention, there is provided a method for distributing banks in a semiconductor memory device, the banks being 2
X+Y
in number, the semiconductor memory device having a 2
A
-bit capacity and including 2
A−B−1
cell array blocks, each including two 2
B
-bit cell arrays, a plurality of column decoders connected respectively to the cell arrays, and a plurality of row decoders, each being positioned between the two cell arrays in each of the cell array blocks and connected in common to them, the method comprising a first step of dividing each of the 2
B
-bit cell arrays horizontally by 2
X
and vertically by 2
Y
into 2
X+Y
cell groups in such a manner that 2
B−X−Y
cells are allocated to each of the 2
X+Y
cell groups; and a second step of defining each of the 2
X+Y
cell groups as a bank section of a corresponding one of the 2
X+Y
banks, where A, B, X and Y are natural numbers.
In accordance with another aspect of the present invention, there is provided a method for distributing banks in a semiconductor memory device, the banks being 2
X+Y−P
in number, the semiconductor memory device having a 2
A
-bit capacity and including 2
A−B−1
cell array blocks, each including two 2
B
-bit cell arrays, a plurality of column decoders connected respectively to the cell arrays, and a plurality of row decoders, each being positioned between the two cell arrays in each of the cell array blocks and connected in common to them, the method comprising a first step of dividing each of the 2
B
-bit cell arrays horizontally by 2
X
and vertically by 2
Y
into 2
X+Y
cell groups in such a manner that 2
B−X−Y
cells are allocated to each of the 2
X+Y
cell groups; and a second step of defining every 2
P
of the 2
X+Y
cell groups as bank sections of a corresponding one of the 2
X+Y−P
banks, where A, B, P, X and Y are natural numbers.
In accordance with still another aspect of the present invention, there is provided a method for distributing banks in a semiconductor memory device, the banks being 2
X+Y+1
in number, the semiconductor memory device having a 2
A
-bit capacity and including 2
A−B−1
cell array blocks, each including two 2
B
-bit cell arrays, a plurality of column decoders connected respectively to the cell arrays, and a plurality of row decoders, each being positioned between the two cell arrays in each of the cell array blocks and connected in common to them, the method comprising a first step of dividing each of the 2
B
-bit cell arrays horizontally by 2
X
and vertically by 2
Y
into 2
X+Y
cell groups in such a manner that 2
B−X−Y
cells are allocated to each of the 2
X+Y
cell groups; and a second step of defining each of the 2
X+Y+1
cell groups in each of the cell array blocks as a bank section of a corresponding one of the 2
X+Y+1
banks, where A, B, X and Y are natural numbers.


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