Semiconductor memory device having a multilayered bitline struct

Details Semiconductor memory device having a multilayered bitline struct Semiconductor memory device having a multilayered bitline struct

1997-06-09

1999-08-03

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365 51, 36523003, 365205, G11C 702

Patent

active

059333804

ABSTRACT:
A semiconductor memory device includes a memory cell array having a plurality of memory cells, the memory cell array being divided into a plurality of blocks, a plurality first bitlines arranged in each of the blocks, the plurality of first bitlines forming a plurality of first bitline pair each having a folded bitline structure with two of the plurality of first bitlines as a basic unit, a plurality second bitlines arranged to correspond to at least one of the blocks and formed above the first bitlines, the plurality of second bitlines forming a plurality of second bitline pair each having a folded bitline structure with two of the plurality of second bitlines as a basic unit, a plurality of sense amplifier circuits, arranged to correspond to the plurality of second bitline pairs, for detecting and amplifying information stored in the memory cells, and a plurality of select circuits for selecting one of two of first bitlines included in one of the plurality of first bitline pairs to selectively connect a selected first bitline with one of two of second bitlines included in one of the plurality of second bitline pairs.

REFERENCES:
patent: 5014241 (1991-05-01), Asakura et al.
patent: 5495440 (1996-02-01), Asakura
patent: 5555203 (1996-09-01), Shiratake et al.
patent: 5610871 (1997-03-01), Hidaka

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