Semiconductor memory device having a multibit test mode

Details Semiconductor memory device having a multibit test mode Semiconductor memory device having a multibit test mode

1999-06-14

2000-05-09

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

365201, G01R 3128, G06F 1100

Patent

active

060618086

ABSTRACT:
In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.

REFERENCES:
patent: 5091884 (1992-02-01), Kagami
patent: 5293386 (1994-03-01), Muhmenthaler et al.
patent: 5416741 (1995-05-01), Ohsawa
patent: 5488578 (1996-01-01), Yamada
patent: 5535161 (1996-07-01), Kato
patent: 5537351 (1996-07-01), Suwa et al.
patent: 5544106 (1996-08-01), Koike
patent: 5548596 (1996-08-01), Tobita
patent: 5555212 (1996-09-01), Toshiaki et al.
patent: 5574729 (1996-11-01), Kinoshita et al.
patent: 5654924 (1997-08-01), Suzuki et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device having a multibit test mode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having a multibit test mode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a multibit test mode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1075706