Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-12-27
2002-05-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S230030
Reexamination Certificate
active
06392942
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a multi-layer interconnection structure. More specifically, the present invention relates to an interconnection structure of a semiconductor memory device suitable for merging with logic.
2. Description of the Background Art
FIG. 27
is a schematic representation of an arrangement of a logic-merged memory. In
FIG. 27
, logic-merged memory
900
includes a logic
902
for performing a prescribed processing, a memory
904
for storing necessary data for logic
902
, and an internal bus
906
for interconnecting logic
902
and memory
904
. Memory
904
is normally formed by a dynamic random access memory (DRAM). Logic
902
and memory
904
are formed on the same semiconductor chip, and internal bus
906
connecting the two can have a sufficiently wide bus width. Therefore, being free from the restrictions of the pin terminals of memory
904
, internal bus
906
can be made to have a sufficiently narrow interconnection line pitch. In addition, internal bus
906
is internal interconnection lines so that each parasitic impedance is small, which allows a high-speed data transfer between logic
902
and memory
904
. Moreover, the parasitic capacitance of the internal interconnection lines of internal bus
906
is small so that the charging/discharging current of a signal line can be reduced in comparison with the case of wiring provided on the board, thereby achieving lower power consumption.
In general, in a general-purpose DRAM, the number of metal interconnection layers used is relatively small, i.e., as in a single metal structure using only one layer of metal interconnection, or a double metal structure using two layers of metal interconnection. The small number of metal interconnection layers keeps the height of the DRAM low, and the step formed between the internal interconnection lines small, while helping to prevent the destruction of a fine-fabricated interconnection/element due to the stress caused in the height direction by interlayer insulating film and the like.
On the other hand, as for a logic circuit, a quadruple metal structure or a quintuple metal structure where the number of the metal interconnection layers used are four or five is employed in order to adapt to higher speeds, and the number of metal interconnection layers is on the increase.
Following this increase in the number of metal interconnection layers, in a logic-merged DRAM also the high speed operation of the logic circuit is given high priority, so that a multi-layer metal interconnection is often used for the logic circuit. For the DRAM region, and particularly for the memory cell array of a DRAM, however, the design resource of a conventional general-purpose DRAM is often utilized without making changes so that a control signal line, an internal data line, and the like are often formed with a single metal structure or a double metal structure.
FIG. 28
is a schematic representation of the interconnection structure of a conventional DRAM. In
FIG. 28
, a memory array is divided into a plurality of memory blocks MBa, MBb, and so on. In memory blocks MBa and MBb, memory cells, not shown, are arranged in a matrix of rows and columns. A main word line MWL is provided extending in the row direction over these memory blocks MBa and MBb. A main word line group MWLS including main word line MWL is formed by a first level aluminum interconnection (
1
Al) line. Main word lines MWL are coupled to sub word lines at a lower layer not shown via respective sub word drivers SWD.
A sense amplifier circuit and a column select circuit are arranged in the region adjacent to memory blocks MBa and MBb in the column direction. In a sense amplifier band where the sense amplifier circuit and the column select circuit are arranged, a sense amplifier control signal line SCTL for controlling the sense amplifier circuit, a sense power-supply line SPSL for transmitting a power-supply voltage to the sense amplifier circuit, and a sub-decode signal line SDL for transmitting a sub-decode signal for selecting a sub word line are arranged extending in the row direction. A sense amplifier band internal interconnection line group SAIG is formed in the first level aluminum interconnection layer.
On-array internal interconnection line groups ARIGa and ARIGb formed by second level aluminum interconnection (
2
Al) lines are provided on memory blocks MBa and MBb, respectively. On-array internal interconnection line groups ARIGa and ARIGb include a power-supply line PSL for transmitting a power-supply voltage VCC or a ground voltage. Power-supply line PSL is coupled to sense power-supply line SPSL and strengthens the power supply for the sense amplifier circuit (i.e., limits the variation in the power-supply voltage and the voltage distribution for the sense amplifier circuit).
A driver band internal interconnection line group SWIG extending in the column direction is arranged in a sub word driver band between memory block MBa and memory block MBb. Driver band internal interconnection line group SWIG includes a local subdecode signal line LSDL coupled to subdecode line SDL, and power-supply line PSL for transmitting the power-supply voltage. On-array internal interconnection line groups ARIGa and ARIGb and driver band internal interconnection line group SWIG are all formed in the second level aluminum interconnection layer. The interconnection structure shown in
FIG. 28
is a double metal structure using the first level aluminum interconnection (
1
Al) layer and the second level aluminum interconnection (
2
Al) layer. When a third level metal interconnection line is used, these upper layer metal interconnection lines are in general all used to strengthen the power-supply lines.
In logic-merged memory
900
shown in
FIG. 27
, logic
902
can be formed with a multi-layer interconnection structure of three or more layers to achieve a higher speed. Since logic
902
and memory (DRAM)
904
are formed on the same semiconductor chip, the same interconnection structure can be applied for memory (DRAM)
904
. Thus, in memory (DRAM)
904
, the same multi-layer interconnection structure as logic
902
can be utilized for circuits such as the control circuit, buffer circuit, and data input/output circuit so that peripheral circuitry capable of operating at a high speed can be realized.
The memory array portion is, however, formed making use of the resources of the conventional DRAM, and these multi-layer interconnection structures are not effectively utilized. As the memory cells are increasingly miniaturized, the pitch for a memory cell row and a memory cell column gets smaller. To accommodate such miniaturization, the layout configuration of the direct peripheral circuitry provided within the memory array, such as a sub word driver and a sense amplifier circuit, becomes more complicated. When circuitry having such a complicated layout is provided, unlike the arrangement in which a relatively simple pattern such as a word line is repeated, the accurate photolithography process cannot be performed due to diffused (irregular) reflection and mutual interference, and so on, of energy rays during the exposure step, which leads to the problem of low production yield.
In addition, sense amplifier control signal line SCTL, as shown in
FIG. 28
, for transmitting a sense amplifier control signal and the like is formed by the first level aluminum interconnection line to which impurities are added in order to bring a greater strength than the second level aluminum interconnection line to the first level aluminum interconnection line. As a result, the electrical characteristic of the first level aluminum interconnection line is degraded from that of the second level aluminum interconnection line. Moreover, in accordance with the miniaturization of the element, the first level aluminum interconnection line has an extremely narrow line width, and when a sense amplifier control signal li
Fujino Takeshi
Noda Hideyuki
Le Thong
McDermott & Will & Emery
Mitsubisishi Denki Kabushiki Kaisha
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