Semiconductor memory device having a memory test circuit

Details Semiconductor memory device having a memory test circuit Semiconductor memory device having a memory test circuit

1990-11-21

1993-02-09

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36518904, 365210, 371 211, G11C 700

Patent

active

051857227

ABSTRACT:
A semiconductor memory device has an array of examined memory cells, and reference memory cells in a column. The examined memory cells in each column and the reference memory cells are connected with respective pairs of complementary bit lines connected with sense amplifiers. Each reference memory cell and the examined memory cells in each row are connected with corresponding word lines. The device also has a line data memory circuit, a bit line select circuit and a plurality of output evaluation circuits connected with the bit line pairs for the examined memory cells. In a test mode, identical data is simultaneously written to the reference and examined memory cells connected with each word line. The line data memory circuit outputs data from the reference memory cell as expected data, in response to which, the bit line select circuit selects one of the bit lines for each of the examined memory cells when the expected data is LOW, and the other of the bit lines when the expected data is HIGH. Each output evaluation circuit simultaneously detects an output from a corresponding examined memory cell via the one bit line or the other bit line selected in accordance with the expected data, and outputs a signal indicating coincidence or non-coincidence between the output signal detected and the expected value. Thus the device tests its own operation through a parallel access to the memory cells.

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Excerpt of a lecture entitled "Parallel Testing Technology for ULSI Memories" made in a National Spring Meeting held by The Institute of Electronics, Information and Communication Engineers, 1989, Spring.

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