Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-04-17
2002-12-24
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S051000, C365S053000, C365S230060
Reexamination Certificate
active
06498763
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of Related Art
It is very important for semiconductor memory devices such as dynamic random access memory (DRAM) to increase the operation speed and to reduce the production cost and power consumption as the chip size becomes miniaturized.
In such a DRAM, a row address and a column address are synchronized in response to control signals and clock signals and then are sequentially inputted through the same package pins. The inputted row address simultaneously activates a plurality of memory cells that are connected with one word line selected by a row decoder. However, since a plurality of the memory cells that are connected with one word line are arranged in a longitudinal direction of the word line, due to a line resistance of the word line, the farther the memory cell is from the row decoder, the more delayed the activation time of the memory cell is. Therefore, an enable time of the word line depends on an activation time of the farthest memory cell from the row decoder. The activation time of the memory cell affects a row access time (tRAC), thereby lowering an operation speed of the semiconductor memory device.
Further, the memory cell has been gradually miniaturized according to a trend of a high integration, and thus a portion of the word line to which the memory cell is connected is made of not a metal but a polycrystalline silicon, whereupon a word line enable time and a charge sharing time, which greatly affect an activation time of the DRAM, become lengthy.
Furthermore, the memory cell array typically includes a plurality of sub-cell arrays. Even though the numbers of the sub-cell array and sub-word line driver are decreased in order to reduce a chip size, since the number of the memory cells that are connected with the word line increases, a word line activation time becomes lengthier.
FIG. 1
is a plan view illustrating a memory cell array of a semiconductor memory device according to a conventional art. A 256M DRAM includes four memory cell arrays. Each of the memory cell arrays has the capacity of 64M bits. As shown in
FIG. 1
, the memory cell array
10
includes
16
memory blocks BLK
0
to BLK
15
and 17 sub-word line drivers SWD
0
to SWD
16
. The sub-word line driver is driven by one row address and includes 8 odd sub-word line drivers SWD
1
, SWD
3
to SWD
15
and 9 even word line drivers SWD
0
, SWD
2
to SWD
16
. Each of the memory blocks includes 4 MOSFET transistors arranged at a crossing point of the 16K sub-word lines SWL and 256 bit line pairs BL/BLB. In other words, one word line SWL is connected with 256 cell transistors, and thus when one word line is selected, 256 cell transistors go to an active state at the same time. The sub-word line is directly connected with a gate electrode of the transistor and is made of polycrystalline silicon.
The sub-word line drivers SWD
0
to SWD
16
are respectively arranged between a pair of the memory blocks. In other words, a pair of the memory blocks shares one sub-word line driver. The sub-word line drivers are connected with 16K metal word lines WL (not shown in
FIG. 1
) that are formed over the cell transistor. The odd sub-word line drivers SWD
1
to SWD
15
are enable-controlled through first enable drivers PXID
0
to PXID
7
, and the even word line drivers SDW
0
to SWD
16
are enable-controlled through second enable drivers PXIDB
0
to PXIDB
8
, respectively. Therefore, each of the sub-word line drivers is enabled through the corresponding enable driver and activates the corresponding sub-word line SWL in response to a word line driving signal transmitted via the metal word line WL.
A row decoder RD is arranged at a location adjacent to the memory block BLK
15
of the cell array
10
. The row decoder RD decodes a row address and generates a first signal PNWEi for activating the selected metal word line WL.
An enable controller PXI provides the first enable drivers PXID
0
to PXID
7
and the second enable drivers PXIDB
0
to PXIDB
8
with enable signals through control lines CL and CLB, respectively.
An operation of the word line activation is explained hereinafter. The row decoder RD decodes a row address to select the first signal PNWEi. Then, enable signals are transmitted from the enable controller PXI to either of the first and second enable drivers PXIDi and PXIDBi, respectively, through either the signal line CL or CLB. The enable signals are conveyed to the nearest sub-word line driver SWD
15
or SWD
16
to the row decoder RD before the others. The enable signals are conveyed to the farthest sub-word line SWD
1
or SDW
0
to the row decoder RD after the others.
Out of 256 cell transistors that are connected with the sub-word line SWL activated by the sub-word line driver SWD
1
, the nearest cell transistor CELL
255
is the first to be activated, and the farthest cell transistor CELL
0
is the last to be activated.
Of 255 cell transistors that are connected with the sub-word line SWL activated by the sub-word line driver SWD
1
, the nearest cell transistor CELL
255
is the first to be activated, and the farthest cell transistor CELL
0
is the last to be activated.
Since the sub-word line SWL is made of polycrystalline silicon that is greater in resistance than a metal, the cell transistor CELL
255
of the sub-word line SWL is activated by the sub-word line driver SWD
1
is activated before the cell transistor CELL
0
of the sub-word line SWL activated by the sub-word line driver SWD
15
. Therefore, as shown in
FIG. 2
, a word line activation time is delayed up -to an activation time of the cell transistor CELL
0
of the sub-word line SWD
1
, thereby increasing a row access time (tRAC) and a row precharge time (tRP).
FIG. 2
is a timing diagram illustrating wave forms of sub-word lines. At this point, the vertical axis denotes voltage, and the horizontal axis represents time.
In case of high-integrated DRAM having the capacity of 1G, 4G, or 16G bits, a delay difference between the earliest cell transistor and the latest cell transistor becomes greater, thereby increasing a word line activation time length.
For the foregoing reasons, there is a need for a semiconductor memory device having a short word line activation time length.
SUMMARY OF THE INVENTION
According to a feature of an embodiment of the present invention, there is provided a semiconductor memory device having a short word line activation time length. According to another feature of an embodiment of the present invention, there is provided a semiconductor memory device having a plurality of memory cell arrays, each of the memory cell arrays having a plurality of memory blocks. Each of the memory blocks has a plurality of transistors. According to another feature of the present invention, the semiconductor memory device further includes a row decoder located adjacent to the memory cell array. According to yet another feature of the present invention, a capacitance of a memory block becomes smaller as the memory block becomes farther from the row decoder.
According to another feature of an embodiment of the present invention, the memory cell array further includes a word line activated by the row decoder. The word line includes a plurality of sub-word lines. Each of the sub-word lines is connected with the plurality of the transistors. A plurality of sub-word line drivers activate the sub-word lines. A plurality of enable drivers enable the sub-word line drivers. An enable controller provides the plurality of the enable drivers with enable signals. One sub-word line of the farthest memory block from the row decoder is connected with 224 transistors, and one sub-word line of the nearest memory block to the row decoder is connected with 288 transistors.
According to another feature of an embodiment of the present invention, each of the memory cell arrays includes 3 memory blocks having 224 transistors per one sub-word line, 3 memory blocks having 240 transistors per one sub-word line, 4 memory blocks havi
Ho Hoai
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
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