Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Patent
1989-10-26
1991-11-19
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Including specified plural element logic arrangement
36518907, 365201, 371 36, G11C 700, G06F 1108
Patent
active
050671111
ABSTRACT:
A semiconductor memory device comprising a first Electrically Erasable Programmable Read Only Memory (EEPROM) cell array, a first row decoder, a first column decoder, two second EEPROM arrays each having a storage area equal in capacity to the specified storage area defined in the first EEPROM array, a second row decoder, a second column decoder, and a majority logic circuit. The first row decoder and the first column decoder access one of the memory cells of the first EEPROM array. The second row decoder and the second column decoder access one of the memory cells of either the second EEPROM array when one of the memory cells of first EEPROM array is accessed. The majority logic circuit carries out a majority logic operation on the data items read from the accessed memory cell of the first EEPROM array and the data items read from the accessed memory cells of the second EEPROM arrays, thereby to determine which data item is to be read out to an external device.
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patent: 4748594 (1988-05-01), Iida
Cioaca et al., "A Million-Cycle CMOS 256K EEPROM," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, pp. 684-692, Oct. 1987.
Asano Masamichi
Iwahashi Hiroshi
Yokoyama Sadayuki
Hecker Stuart N.
Kabushiki Kaisha Toshiba
Lane Jack A.
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