Semiconductor memory device having a layout pattern adjusted inp

Details Semiconductor memory device having a layout pattern adjusted inp Semiconductor memory device having a layout pattern adjusted inp

1999-06-28

2000-11-28

Elms, Richard

Static information storage and retrieval

Read/write circuit

Signals

365214, 3652257, 365149, G11C 700

Patent

active

061543950

ABSTRACT:
An object of the invention is to provide a semiconductor memory device suppressing variations in input terminal capacitances of address input terminals and control signal input terminals and enabling a high-speed access. The invention arranges a plurality of terminal capacitance adjusting elements each of which is composed of an ESD element (punch-through element) 6a, 6b or 6c and a terminal capacitance adjusting terminal capacitance element 7a, 7b or 7c through connection changeover aluminum wiring 8a, 8b and 8c in the course of an aluminum wiring 4 from an input terminal to an internal circuit.

REFERENCES:
patent: 4872042 (1989-10-01), Maeda et al.
patent: 5327392 (1994-07-01), Ohtsuka et al.
patent: 5973954 (1999-10-01), Wu et al.

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