Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2003-05-22
2004-12-14
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S189050
Reexamination Certificate
active
06831852
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor device. Particularly, the present invention relates to a semiconductor device including a latch circuit.
2. Description of the Background Art
Conventionally, a DRAM (Dynamic Random Access Memory) is known as one type of semiconductor memory device. Also, a SRAM (Static Random Access Memory) is known as another type of semiconductor memory device. (Refer to Document 1 (Japanese Patent Laying-Open No. 3-34191) and Document 2 (Japanese Patent Laying-Open No. 63-285794).)
In such conventional DRAMs, the charge stored in a capacitor will leak from a storage node to a semiconductor substrate through a well at an elapse of a predetermined period of time, whereby the charge in the capacitor is lost. Leakage and loss of charge implies that information is lost. To prevent such loss, a refresh operation to restore the charge of a capacitor is effected at a predetermined cycle before the charge is completely lost in a DRAM. This requirement for a refresh operation of the circuitry as well as the requirement for constant operation to retain the storage even in a standby state has become the major factor of increasing the power consumption in a DRAM. A “standby state” implies a state where no access is made from an external source and only power supply is applied to the memory cell.
The SRAM is known as a semiconductor memory device that does not require the above-described refresh operation. However, a SRAM is disadvantageous in that six transistors per one memory cell must be formed on a silicon substrate. There was a problem that the memory size is extremely larger than that of a DRAM.
The conventional SRAM is also disadvantageous in that the charge capacity of the storage node is small, susceptible to soft errors. “Soft error” is a phenomenon in which alpha particles entering the silicon substrate generate of electron-hole pairs to alter the stored charge in the storage node, resulting in loss of stored data.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device that does not require a refresh operation.
Another object of the present invention is to provide a semiconductor device of high reliability, more tolerant to the above-described soft error phenomenon in a semiconductor device.
According to an aspect of the present invention, a semiconductor memory device includes: a capacitor storing charge according to a logic level of binary information, located above a semiconductor substrate, and having a storage node; an access transistor controlling input/output of charge stored in the capacitor, located at the surface of the semiconductor substrate, and having a pair of impurity regions, one of the pair of impurity regions being connected to the capacitor; a latch circuit retaining the potential of the storage node of the capacitor, located on the semiconductor substrate; and a bit line connected to the other of the pair of impurity regions of the access transistor. At least a portion of the latch circuit is provided above the bit line.
In the semiconductor memory device of the above-described structure, a latch circuit to retain the potential of the storage node of the capacitor is provided. It is no longer necessary to conduct a refresh operation since the potential of the capacitor is retained by the latch circuit. Since the charge corresponding to a logic level of binary information is held by a capacitor, resistance to soft error caused by alpha particles is improved as compared to a semiconductor device having charge stored in the storage node as in a conventional SRAM.
Furthermore, the provision of at least a portion of the latch circuit above the bit line allows the semiconductor to be reduced in size.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5805494 (1998-09-01), El-Kareh et al.
patent: 6236598 (2001-05-01), Chou
patent: 6271569 (2001-08-01), Ishigaki et al.
patent: 63-285794 (1988-11-01), None
patent: 3-34191 (1991-02-01), None
patent: 6-216345 (1994-08-01), None
Fujii Yasuhiro
Ishigaki Yoshiyuki
Koga Tsuyoshi
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