Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2007-08-14
2007-08-14
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S208000, C365S207000, C365S051000, C257S347000
Reexamination Certificate
active
10621357
ABSTRACT:
The disclosure concerns a semiconductor memory device including a plurality of transistors. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage. A sense amplifier is provided for a plurality of bit lines connected to drain diffusion regions of the transistors, one of the bit lines being connected to the sense amplifier. The first data state is a state in which impact ionization is generated near a drain junction by operating the transistor and in which excessive majority carriers produced by this impact ionization are held in the semiconductor layer. The second data state is a state in which a forward bias is applied between the semiconductor layer and the drain diffusion region to extract the excessive majority carriers from within the semiconductor layer to the drain diffusion region.
REFERENCES:
patent: 4090254 (1978-05-01), Ho et al.
patent: 4250569 (1981-02-01), Sasaki et al.
patent: 5218217 (1993-06-01), Oda et al.
patent: 5448513 (1995-09-01), Hu et al.
patent: 5712501 (1998-01-01), Davies et al.
patent: 5770881 (1998-06-01), Pelella et al.
patent: 5774411 (1998-06-01), Hsieh et al.
patent: 5784311 (1998-07-01), Assaderaghi et al.
patent: 5870329 (1999-02-01), Foss
patent: 6111778 (2000-08-01), MacDonald et al.
patent: 6621725 (2003-09-01), Ohsawa
patent: 6693326 (2004-02-01), Adan
patent: 6825524 (2004-11-01), Ikehashi et al.
patent: 1180799 (2002-02-01), None
patent: 56-78156 (1981-06-01), None
patent: 56-119986 (1981-09-01), None
patent: 03-171768 (1991-07-01), None
patent: 5-86864 (1993-12-01), None
patent: 5-87027 (1993-12-01), None
patent: 8-213624 (1996-08-01), None
patent: 9700227 (1997-01-01), None
English translation of JP Publication 5-86864.
English translation of JP Publication 5-87027.
Hsing-jen Wann et al., “A Capacitorless DRAM Cell on SOI Substrate”, IEEE, 1993, p. 26.4.1-26.4.4.
Marnix R. Tack, et al., “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures”, IEEE Transactions On Electron Devices, May 1990, p. 1373-1382, vol. 37, No. 5.
John E. Leiss, et al., “dram Design Using the Taper-Isolated Dynamic RAM Cell”, IEEE Transactions On Electron Devices, Apr. 1982, p. 707-714, vol. Ed-29, No. 4.
Patent Abstracts of Japan, Publication No. 56078156, Publication Date Jun. 26, 1981, 1 page.
Patent Abstracts of Japan, Publication No. 56119986, Publication Date Sep. 19, 1981, 1 page.
Patent Abstracts of Japan, Publication No. 08213624, Publication Date Aug. 20, 1996, 1 page.
Marix R. Tack, et al., “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures”, IEEE Transactions on Electron Devices, vol. 37, No. 5, May 1980, pp. 1373-1382.
Shigeki Tomishima, et al., “A Long Data Retention SOI-DRAM with the Body Refresh Function”, 1996 Symposium on VLSI Circuits Digest of Technical Papres, pp. 198-199.
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Tran Andrew Q.
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