Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2007-07-10
2007-07-10
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S149000, C365S051000, C365S063000, C257S350000, C257S347000
Reexamination Certificate
active
11199185
ABSTRACT:
A semiconductor memory device includes: a semiconductor layer which is formed on an insulating layer; a plurality of transistors which are formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs which are connected to the source regions of the transistors; drain contact plugs which are connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs; and bit lines which are formed so as to cross the word lines and which are connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage.
REFERENCES:
patent: 4090254 (1978-05-01), Ho et al.
patent: 4250569 (1981-02-01), Sasaki et al.
patent: 5218217 (1993-06-01), Oda et al.
patent: 5448513 (1995-09-01), Hu et al.
patent: 5712501 (1998-01-01), Davies et al.
patent: 5770881 (1998-06-01), Pelella et al.
patent: 5774411 (1998-06-01), Hsieh et al.
patent: 5784311 (1998-07-01), Assaderaghi et al.
patent: 5870329 (1999-02-01), Foss
patent: 6111778 (2000-08-01), MacDonald et al.
patent: 6621725 (2003-09-01), Ohsawa
patent: 6693326 (2004-02-01), Adan
patent: 6825524 (2004-11-01), Ikehashi et al.
patent: 1180799 (2002-02-01), None
patent: 56-78156 (1981-06-01), None
patent: 56-119986 (1981-09-01), None
patent: 03-171768 (1991-07-01), None
patent: 5-86864 (1993-12-01), None
patent: 5-87027 (1993-12-01), None
patent: 8-213624 (1996-08-01), None
patent: 9700227 (1997-01-01), None
Hsing-jen Wann et al., “A Capacitorless DRAM Cell on SOI Substrate”, IEEE, 1993, p. 26.4.1-26.4.3.
Marnix R. Tack, et al., “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures”, IEEE Transactions On Electron Devices, May 1990, p. 1373-1382, vol. 37, No. 5.
John E. Leiss, et al., “dram Design Using the Taper-Isolated Dynamic RAM Cell”, IEEE Transactions On Electron Devices, Apr. 1982, p. 707-714, vol. Ed-29, No. 4.
Patent Abstracts of Japan, Publication No. 56078156, Publication Date Jun. 26, 1981, 1 page.
Patent Abstracts of Japan, Publication No. 56119986, Publication Date Sep. 19, 1981, 1 page.
Patent Abstracts of Japan, Publication No. 08213624, Publication Date Aug. 20, 1996, 1 page.
Marix R. Tack, et al., “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures”, IEEE Transactions on Electron Devices, vol. 37, No. 5, May 1980, pp. 1373-1382.
Shigeki Tomishima, et al., “A Long Data Retention SOI-DRAM with the Body Refresh Function”, 1996 Symposium on VLSI Circuits Digeest of Technical Papres, pp. 198-199.
English translation of JP 5-86864.
English translation of JP 5-87027.
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