Semiconductor memory device having a floating gate

Details Semiconductor memory device having a floating gate Semiconductor memory device having a floating gate

1990-04-27

1992-01-28

James, Andrew J.

Static information storage and retrieval

Magnetic bubbles

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357 236, 357 51, 365185, H01L 2968, H01L 2978, H01L 2702

Patent

active

050847457

ABSTRACT:
A semiconductor memory device includes first and second n.sup.+ -type regions formed in the surface area of a p-type substrate; a floating gate insulatively formed over a channel region between the first and second n.sup.+ -type regions; and a control gate disposed to face the floating gate. The area of the portion of the control gate which faces the floating gate is set to be smaller than the effective area of the portion of the floating gate which faces an active region including the first and second n.sup.+ -type regions and channel region.

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Johnson et al., "A 16Kb Electrically Erasable Nonvolatile Memory," IEEE International Solid-State Circuits Conference, ISSCC, Feb. 14, 1980.
Yeargain et al., "A High Density Floating-Gate EPROM Cell," Technical Digest of Int. Electron Devices Meeting, p. 24, 1981.

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