Semiconductor memory device having a ferroelectric memory...

Details Semiconductor memory device having a ferroelectric memory... Semiconductor memory device having a ferroelectric memory...

1999-10-13

2001-07-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S230060, C365S117000, C365S205000, C365S189011

Reexamination Certificate

active

06262910

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, relates to a nonvolatile semiconductor memory device for storing information depending upon a polarization state of a ferroelectric material intervening between ferroelectric capacitor electrodes.
(2) Description of the Related Art
As follows is a description of a conventional ferroelectric memory device with reference to FIG.
1
.
Memory cells MC arranged in an array have a capacitance C for storing information make use of ferroelectric material (hereinafter referred to as “capacitor C”) and a MOS transistor Q, respectively, and are arranged in a matrix so as to form a memory cell array
30
to enable to write, read and erase of the information of the memory cell MC.
With the memory cell array
30
, to a word line (WL
0
, WL
1
. . . ) is connected in common a gate terminal of the transistor Q of the memory cell MC in the same column, and to a plate line (PL
0
, PL
1
. . . ) is connected in common one of the electrodes of the capacitor C of the memory cell in the same column, and word lines WL and plate lines PL are alternately arranged one by one.
Moreover, a bit line (BL
0
, /BL
0
, BL
1
, /BL
1
. . . ) is connected in common to either the drain or source of the transistor of the memory cell in the same row. Therefore, memory cells are arranged in a matrix as a whole, corresponding to nodes of bit lines BL, /BL, word lines WL and plate lines PL.
In
FIG. 1
, of a plurality of bit lines arranged in parallel to each other in the row direction, a pair of adjacent bit lines BL and /BL are shown together with a construction in the vicinity thereof. With respect to a bit line BL of the pair of bit lines BL and /BL, the other bit line /BL is also referred to as a “complementary bit line”. In the following description (including the drawings), as a symbol showing the complementary bit line, there is used “/BL” or “BL” with an upper line “
--
”, but both of them are used in the same meaning.
One end of the bit line BL and the complementary bit line /BL extending in the row direction of the memory cell MC is connected to a sense amplifier
31
for amplifying and detecting the potential difference between the bit line BL and the complementary bit line /BL.
Moreover, as shown in
FIG. 1
, the above described each bit line BL, /BL and plate line PL are connected to a bit line potential supply circuit
32
and a plate potential supply circuit
33
, respectively, for supplying optional predetermined potential for each line, and a plurality of memory cells MC are connected between the above described adjacent bit line BL and /BL.
Next is a description of a method for writing binary data “1” in a conventional memory cell having the above described memory array construction, taking an example of a method for giving optional certain potential to the plate line PL in FIG.
2
A.
The method for writing data “1” is performed in the following manner, as shown in FIG.
2
A. That is to say, positive power supply voltage Vcc is supplied to a bit line BL corresponding to a memory cell MC to be written, and at the same time, potential of the ground level is supplied to a complementary bit line /BL. Then a corresponding word line WL is set to “H” level, and MOS transistors Q
1
and Q
2
included in the memory cell MC to be written are made “ON”, that is, drain and source are connected to supply the power supply voltage Vcc to one of the electrodes of a capacitor C
1
.
Here, optional predetermined potential Vp has been already supplied to a corresponding plate line PL, since the power is switched on, and voltage at a level corresponding to the power supply voltage Vcc is applied to the bit line BL, to thereby generate electric field EVcc
1
, occurring between the both electrodes of capacitor C
1
, at a level determined by subtracting the predetermined potential Vp of the plate line PL from Vcc. With this electric field, electric charge corresponding to the polarization Ps
1
shown in
FIG. 3A
is stored in the capacitor C
1
to thereby store the polarization state.
On the other hand, since voltage of the ground potential level has been supplied to the complementary bit line /BL, electric field EVcc
2
of a level subtracting the ground potential from the optional predetermined potential Vp of the plate line PL is generated between both electrodes of the capacitor C
2
. With this electric field, polarization Ps
2
shown in
FIG. 2A
is stored in the capacitor C
2
to thereby store the polarization information.
When the word line WL is made “OFF”, since optional predetermined potential Vp has been supplied to the plate line PL, it is necessary to make the potential of the opposite pole equal. Therefore, it is necessary to periodically refresh the electrode of the capacitor C
1
on the side connected to the bit line BL and to periodically refresh the electrode of the capacitor C
2
on the side connected to the complementary bit line /BL.
In this case, if it is assumed that both poles of the capacitor have the same potential, the electric field between both poles becomes 0, and polarization Pr
1
(
FIG. 3A
) remains in the capacitor C
1
, and polarization Pr
2
(
FIG. 4A
) remains in the capacitor C
2
.
Moreover, when the power supply voltage Vcc is not provided (specifically, when the power supply voltage Vcc is 0V), the potential of both poles of the capacitor is the ground potential level, and polarization Pr is stored.
In the above description, write of data “1” has been explained. Write of data “0” is realized by reversing the voltage level supplied to the bit line BL and the complementary bit line /BL in the case of data “1” described above. That is to say, the ground potential level is supplied to the bit line BL, and the power supply voltage Vcc is supplied to the complementary bit line /BL, thereby residual polarization Pr
1
remains in the capacitor C
2
, contrary to the case of writing the above data “1”, and residual polarization Pr
2
remains in the capacitor C
1
. Hence, data “0” is written in the memory cell.
Furthermore, read of the written data is performed as described below.
First, prior to the read operation, as shown in
FIG. 2B
, the bit line BL and the complementary bit line /BL are discharged to the ground potential level, then subsequently, the potential of the word line WL is made to be “H” level, to thereby make the MOS transistors Q
1
and Q
2
ON, to start the read operation. At this time, the potential of the plate line PL is always the optional predetermined potential Vp.
Then, in the case of reading data “1”, the MOS transistor Q
1
is ON, and the voltage of the ground potential level applied to the capacitor C
1
, to thereby generate the electric field in the opposite direction to that of the write case between the potential Vp of the plate line PL and the capacitor C
1
. Thereby, the polarization state of the ferroelectric film included therein is inverted, to inverse the storage state of polarization in the capacitor C
1
.
On the other hand, since the electric field in the same direction as that of the write case is formed in the capacitor C
2
, polarization of the ferroelectric film included therein is not inverted. Hence, inversion of the storage state of polarization in the capacitor C
2
is not caused. However, the storage amount of polarization changes slightly, with application of the electric field.
Then, electric charge in an amount corresponding to the change of the stored polarization in the capacitors C
1
and C
2
flows into the bit line BL and the complementary bit line /BL. The potential of the bit line BL becomes slightly larger than that of the complementary bit line /BL, due to the difference in an amount of electric charge flowing therein. By amplifying and detecting the potential difference between the bit line BL and the complementary bit line /BL with the sense amplifier
31
in
FIG. 1
, the stored data “1” is read.
In the case of reading data “0”, the electric field in the opposite direction to that of the wri

Affiliated with

Also associated with

Rating

Semiconductor memory device having a ferroelectric memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having a ferroelectric memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a ferroelectric memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2453691