Semiconductor memory device having a DRAM cell structure and...

Details Semiconductor memory device having a DRAM cell structure and... Semiconductor memory device having a DRAM cell structure and...

2005-03-15

2005-03-15

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S207000, C365S233500

Reexamination Certificate

active

06868027

ABSTRACT:
A semiconductor memory device includes a memory cell array including a plurality of memory cells having a DRAM cell structure and is treated as a SRAM memory device without controlling the data refreshing cycle for the memory cells. The refreshing cycle is separated into a read operation and a write operation, which sandwich therebetween a read/write operation for the input address of the memory cell. The data read in the refreshing cycle is saved in a refreshing sense amplifier during the read/write operation and stored in the memory cell after the read/write operation.

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