Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-12-07
2004-04-20
Gossage, Glenn (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S167000, C365S189070, C365S233100
Reexamination Certificate
active
06725325
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having an internal address generation function and late write function such as DDR (double data rate) SRAM (static random access memory), and to a data processing system utilizing this semiconductor memory device as a main memory or cache memory.
The clock-sync type SRAM of SDR (single data rate) reads or writes one piece of data in each clock cycle. The read operation is started by supplying an address signal from the outside, but data is not actually read out until the read operation is settled. The operation of writing to memory cells is started by supplying write data and a write address. At this time, a fast SRAM of short access cycle utilizes the late write function so that the read out data and the write data fed from the outside in the next memory cycle cannot collide with each other at an IO (input/output) pin. The late write function enables the operation that in a write cycle the write data is fed in the last part of the write cycle, and the write data and write address fed from the outside in that write cycle are stored in latch circuits, and in the next write cycle the latched data is written in the latched address. Thus, under the use of this late write function, when the read operation is ordered to read data at the same address as the latched address stored in the late write register, the latched data in that late write register is read out since the data at this address is not yet written in the memory cells.
The clock-sync type SRAM of DDR (double data rate) in the read cycle receives an external address and internally generates a burst address as the subsequent address at each clock cycle, and it reads data in parallel from each of the external address and burst address of a memory array and serially supplies the read data to the outside in synchronism with the 1/2 cycle of the clock signal. In the write cycle, the write data serially fed in synchronism with the 1/2 cycle of the clock signal are written in parallel in the memory array on the basis of the external address and burst address.
SUMMARY OF THE INVENTION
However, the present inventor discovered that the late write function in the DDR clock-sync type SRAM may cause error when also used in the SDR clock-sync type SRAM without change. In other words, if the latched data in the late write register is read out only when the read address coincides with the external address latched in the late write register as in the SDR type, data will be read out incorrectly from the memory cell array on the data associated with the burst address that is to be rewritten, but not yet rewritten. In short, even though the read address coincides with the burst address in the previous write cycle, the data associated with the burst address that matches with the read address must be read out.
The DDR clock-sync type SRAM is described. in JP-A-11-195296. In this document, the external address and burst address are grasped from the standpoint of even address and odd address, and the burst address is generated by use of a counter. Then, the burst address is also compared directly with the external address in order to prevent the above wrong operation.
However, since the burst address internally generated from the standpoint of even/odd address is used in the technique of the above document, storage means for holding the burst address is additionally needed. Also, since the even/odd of the burst address varies according to that of the external address, the scale of the logic for preventing the wrong read operation due to the late write function becomes relatively large.
Accordingly, it is an object of the invention to reduce the scale of the logic for the generation of burst address and the prevention of wrong operation in the memory having the late write function and DDR mode.
The above and other objects, and novel features of the invention will become clear from the description of this specification and the accompanying drawings.
Typical examples of the invention disclosed in this application will be outlined below.
The semiconductor memory device has a double data rate (DDR) mode in which it is possible to make an internal parallel operation on a specified memory address externally fed and a secondary memory address made different from the specified memory address by changing the last two or more bits, and an external serial input/output operation suitable with the internal parallel operation so that when an address comparing means of the semiconductor memory device detects that the specified memory address or the secondary memory address for a reading operation matches the specified memory address latched in an address register of the semiconductor memory device or the secondary memory address in a preceding writing operation, data corresponding to the matching memory address can be fed to the outside from a data register of the semiconductor memory device. At this time, the address comparing means includes a first comparison logic circuit formed of combined circuits by which the last two or more bits of the specified memory address for a reading operation can be compared with the last two or more bits of the specified memory address for the preceding writing operation, a second comparison logic circuit formed of combined circuits that can detect if the bits other than the last two or more bits of the specified memory address for a reading operation respectively match the bits other than the last two or more bits of the specified memory address for the preceding writing operation, and a third comparison logic circuit formed of combined circuits which can detect that, when a match is obtained as the result from the second comparison logic circuit, the last two or more bits of the specified memory address or the secondary address for a reading operation match the last two or more bits of the specified memory address or the secondary memory address for the preceding writing operation, on the basis of the result from the first comparison logic circuit.
Even when the read address matches the burst address of the preceding write cycle, the address comparing means causes the read data of the matched burst address to be produced in response to this read address, thus preventing the erroneous operation due to the fact that the data to be scheduled to be rewritten but not yet written in memory cells are not read out because of the late write function.
In addition, the address comparing means for that purpose includes first through third logic circuits each of which is fundamentally formed of combined circuits. Also, the secondary memory address is not directly produced, and does not need to be directly held in a sequence circuit. Thus, the DDR-mode memory having the late write function can be reduced in its logic scale for burst address generation and malfunction prevention.
The DDR mode makes it possible that, in response to an order to perform the reading operation, data in the specified memory address and the secondary memory address are read in parallel from a memory cell array of the semiconductor memory device and then serially supplied to the outside with a period of 1/2 cycle of a clock signal, and it may be an operation mode in which, in response to an order to perform the writing operation, write data in the data register can be written in the specified memory address held in the address register and the secondary memory address in parallel, write data serially fed from the outside with a period of 1/2 cycle of the clock signal can be newly latched in the data register, and the specified memory address for the latched data can be newly latched in the address register.
The present invention is most suitable for SRAM of relatively short access cycle if it is based on the late write function, and in that case the memory cell array has static type memory cells arranged in a matrix shape.
More specifically, when the last two or more bits are the last two bits, the memory cell array has two memory mats. An address decoder of the semiconduct
Agari Takeshi
Mitsumoto Kinya
Nishiyama Masahiko
Antonelli Terry Stout & Kraus LLP
Gossage Glenn
Renesas Technology Corp.
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