Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-09-12
2001-08-28
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S205000, C365S154000
Reexamination Certificate
active
06282133
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device having a delay circuit for generating a read timing of a sense amplifier in the memory device. The present invention also relates to a general semiconductor device having such a delay circuit.
DESCRIPTION OF A RELATED ART
It is generally difficult to determine the timing of data latch in a large-scale/high-speed semiconductor device such as a SRAM and an asynchronous semiconductor memory device. This difficulty results in part from the timing difference generally involved between signals supplied from a large number of memory cells disposed at different positions. It is proposed in JP-A-6-170998, for example, that data be latched by a sense amplifier in a semiconductor memory device based on the timing of the data having a largest time delay.
More specifically, the asynchronous memory device described in the publication has a plurality of dummy memory circuits each having a delay characteristic similar to the delay characteristic of memory circuits. The memory device starts for precharging at the timing of an internal synchronizing signal, and stops the precharging at the timing of a precharge stop signal supplied from the dummy memory circuits. The precharge stop signal is delayed corresponding to the propagation delay of the signal from one of the dummy memory circuits located at the most distant position to generate a data latch signal which determines the latch timing of the read data by the sense amplifier. The delay time is generated by a plurality of inverters successively cascaded or a combination of resistors and capacitors.
The technique for determining the latch timing by the sense amplifier is also described in a literature, presented by Kazumasa Ando, Keiichi Higeta and Yasuhiro Fujimura and entitled“A 0.9-ns-access, 700-MHz SRAM Macro using a Configurable Organization Technique with an Automatic Timing Adjuster”, in IEEE“1998 Symposium on VLSI Circuits Digest of Technical Papers”, pp182-183.
In general, the latch timing should be designed based on o the memory cell which is located most distant, or located near the distal ends of the word line and the bit line, to obtain an activation delay for the sense amplifier corresponding to the largest read time. In this case, however, the timing margin is excessively large to a memory cell which is located nearer than the recited memory cell. Thus, in the automatic timing adjuster described in the literature, the phase of the bit line signal (dummy bit signal) Vd supplied from the dummy cell is compared in a phase comparator against the phase of the sense amplifier activation signal (control clock signal) Vs, and a 6-bit counter which is controlled based on the results of the comparison in the phase comparator outputs a delay control signal which controls the delay time Vs in a variable delay circuit for 64 steps.
The delay time in the dummy bit signal Vd is an analog signal, whereas the control clock signal Vs which determines the latch timing of the sense amplifier must be a digital signal. Thus, the counter converts the analog delay time into a digital data and outputs the digital delay time Vs to the variable delay circuit.
A new delay is generated in the counter, however, when the counter converts the analog signal to a digital signal. Thus, the counter modifies the count therein based on the results of the comparison between the output signal Vs from the variable delay circuit and the dummy bit signal Vd, whereby the delay time included in the control clock signal Vs for the sense amplifier is controlled.
In the technique described in the literature, there is a problem in that an irregularity or fluctuation such as caused by the fabrication process or a temperature change prevents generation of an optical timing signal Vs. In addition, there arises a similar problem if the waiting time is unstable before the delay time is changed based on the fundamental clock signal and the count in the counter. Furthermore, the circuit scale of the memory device becomes large due to provision of the comparator and the counter.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a delay circuit which is capable of generating an optimum delay time providing an optimum timing of the data latch in a large scale integrated semiconductor device such as a SRAM.
The present invention provides a semiconductor memory device including a memory cell array including a plurality of memory cells, an address decoder for decoding an address signal to select one of the memory cells, a read circuit for responding to a sense amplifier enable signal to latch read data from the one of the memory cells at a first timing, a delay circuit for responding to selection of the one of the memory cells to generate a delay signal for specifying the first timing, the delay signal having an delay time reflecting an irregularity in a characteristic of either of pMOSFET and nMOSFET in the memory device.
In accordance with the delay circuit of the present invention, since the delay time reflects an irregularity in a characteristic of either of pMOSFET and nMOSFET in the memory cell, the sense amplifier latches read data from a selected memory cell at an optimum timing irrespective of an irregularity or fluctuation in a characteristic of the memory cells caused by the fabrication process or a temperature change.
REFERENCES:
patent: 5377151 (1994-12-01), Komuro
patent: 5835423 (1998-11-01), Harima
patent: 6-170998 (1994-06-01), None
A 0.9-ns-access, 700-MHz SRAM Macro using a Configurable Organization Technique with an Automatic timing Adjuster, in IEEE 1998 Symposium on VLSI Circuits Digest of Technical Papers pp 182-183.
Nakagawa Atsushi
Takahashi Hiroyuki
Hoang Huan
NEC Corporation
LandOfFree
Semiconductor memory device having a delay circuit for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device having a delay circuit for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a delay circuit for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2528822