Semiconductor memory device having a delay circuit

Details Semiconductor memory device having a delay circuit Semiconductor memory device having a delay circuit

2007-02-20

2007-02-20

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S194000, C365S203000

Reexamination Certificate

active

10907905

ABSTRACT:
A semiconductor memory device having a delay circuit, the delay circuit is constructed in order for a refresh operation and a normal operation to have different delay paths such that a minimum tRAS (Active to Precharge command period) delay time of the refresh operation to which tRFC (Auto Referesh to Active/Auto Referesh command period) is applied is longer than a minimum tRAS delay time of a normal operation to which tRC (Active to Active/Auto Refresh command period) is applied. Thus, a greater noise margin is secured in tRFC in a refresh operation being the worst situation of a DRAM. Accordingly, the probability that fail can occur is reduced and the yield upon test is thus improved.

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