Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
1998-11-24
2001-02-13
Zarabian, Amir (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S191000, C365S189011, C365S189050, C365S233100
Reexamination Certificate
active
06188616
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device that determines a write pulse width timing.
2. Background of the Related Art
FIG. 1
is a block diagram showing a related art semiconductor memory device. The related art semiconductor memory device includes a WCD signal generating part
11
outputting a logical product, which is a write control driving signal WCD, upon application of a write enable signal WET from a pad PAD (not shown). A WCDN generating part
13
produces a signal WCDN for controlling a data input part upon receipt of the WCD signal, a chip selection signal CS, and a signal Z-DEC. A data input part
15
outputs a logical product, which is high-level data and low-level data, to a corresponding memory cell upon application of the write enable signal WET from the pad PAD.
The signal Z-DEC informs the WCDN generating part
13
which cell of cells defined by blocks is selected. The WCD signal generating part
11
includes an inverter INT
1
inverting the applied write enable signal WET, and an inverter INT
2
inverting a signal output from inverter INT
1
. A NAND gate NAND
1
outputs a logical product of an output signal of inverter INT
2
and write enable signal WET, and an inverter INT
3
inverts an output signal of the NAND gate NAND
1
.
The data input part
15
includes an inverter INT
4
inverting applied data, a NOR gate NOR
1
performing a NOR operation with respect to an output signal of inverter INT
4
and the WCDN signal, and a NOR gate NOR
2
performing a NOR operation with respect to the applied data signal and the WCDN signal. Inverters INT
5
and INT
6
respectively invert an output signal of each of the NOR gates NOR
1
and NOR
2
, and an inverter INT
7
inverts an applied signal CWEN. A transfer gate TG
1
is interposed between input and output terminals of the inverter INT
7
, and a transfer gate TG
2
is connected in series to the transfer gate TG
1
.
The transfer gate TG
1
produces high-level data, and the transfer gate TG
2
outputs low-level data. The signal CWEN is a control signal and serves to turn on transfer gates TG
1
and TG
2
when storing data in a cell.
The operation of the related art memory device will now be described. As shown in
FIGS. 2A-2E
, the WCD signal generating part
11
generates the write control driving signal WCD upon application of the write enable signal WET from the pad PAD. When comparing the point of disabling write enable signal WET to that of disabling write control drive signal WCD, there exists a delay time td. The write control driving signal WCD is an internal enable signal WCD necessary for writing data to a cell. Thus, the width of write control driving signal WCD and the points (i.e., timing) of enabling and disabling the WCD signal are important.
The WCDN generating part
13
transmits the signal WCDN to the data input part
15
upon application of the signals WCD and Z-DEC, which is not depicted in FIG.
2
. The data input part
15
writes data to a selected cell under control of the signal WCDN. Accordingly, it is necessary to either advance the point of enabling signal WCD or delay the point of disabling signal WCD to improve the accuracy and speed of the write pulse timing. Delaying the point of the disabling signal WCD causes a delay in the point of disabling the signal WCDN, which adversely affects the write recovery timing. As described above, the write pulse width timing (WPT) may be improved by advancing the point of enabling signal WCD but this technique also has a restriction. The enabling point cannot be advanced too much because of the address setup time. In conclusion, the point of writing data to a cell equals the time when the WCDN generating part
13
produces the signal WCDN on receipt of the signal WCD.
In a case where the power supply voltage transitions to a low level, the point of disabling signal WCD cannot be delayed. In repetition of data write and data read, it is required to disable the signal WCD as soon as possible. Otherwise, the data write timing changes to the data read timing even though writing data to a cell is not completely finished. Thus, delaying the point of the disabling signal WCD adversely affects the write recovery timing.
The above-described related art semiconductor memory device has various disadvantages. In the related art semiconductor memory device there is a time margin or period in the write recovery timing when the power supply voltage attains a low level compared to when the power supply voltage attains a high level, and it is necessary to advance the point of enabling signal WCD in order to compensate for a write pulse width timing (TWP). However, there is a limit to advancing the point of enabling signal WCD because of the address setup timing, which makes it impossible to realize a high speed static random access memory. Further, in the related art device, the points of enabling and disabling signal WCD are not controlled according to the power supply voltage level, which reduces the efficiency of the semiconductor memory device.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a semiconductor memory device that increases a write pulse width timing efficiency.
Another object of the present invention is to provide a semiconductor memory device for a high speed static random access memory.
Another object of the present invention is to provide a semiconductor memory device that determines write pulse width timing based on high or low level power supply voltage characteristics when writing data.
Another object of the present invention is to provide a semiconductor memory device that delays a write control signal timing when the power supply voltage attains a low level, and advances the write control signal timing when the power supply voltage attains a high level.
To achieve at least these objects and other advantages in a whole or in parts, and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device of the present invention includes a write pulse width compensating circuit that compensates a write control drive signal based on a power supply voltage, a first generating circuit that receives the write control drive signal, a first selection signal and a second selection signal and outputs a control signal for a selected cell and a data input circuit that receives data and writes the data to the selected cell based on application of the data and the control signal.
To further achieve these objects and other advantages in a whole or in parts, a write pulse width compensating circuit is provided according to the present invention that includes a write enable delay circuit that receives a write enable signal and outputs a delayed write enable signal, a voltage sensing circuit that determines a power supply voltage and outputs a delay selection signal and a generating circuit that receives the delayed write enable signal, the write enable signal and the delay selection signal and produces a write control drive signal based on the power supply voltage.
To further achieve these objects and other advantages in a whole or in parts, a write pulse width compensating circuit is provided according to the present invention that includes a first transistor with a control electrode receiving a chip enable signal and a second electrode coupled to the power supply voltage, a transfer gate enabled by an output signal of the voltage sensing circuit, an second transistor with a control electrode that receives the power supply voltage and a first electrode coupled to a ground voltage, a first logic
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Nguyen Vanthu
Zarabian Amir
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