Semiconductor memory device having a CMOS sense amplifier

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

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365149, G11C 700, G11C 1124

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047991976

ABSTRACT:
A semiconductor memory device comprises a memory cell array comprising memory cells; a plurality of pairs of bit lines which are coupled to the memory cells and a data bus, each bit line being divided into at least two pairs of bit line parts; at least one sense amplifier provided between the pairs of bit line parts in each of the pairs of bit lines, for sensing a difference in potential between bit line parts in each pair, the sense amplifier being formed with complementary metal oxide semiconductor transistors; and at least a pair of transfer gates provided between a non-data bus side and a data bus side of the sense amplifier, the pair of transfer gates being held in an off-state when the sense amplifier is activated.

REFERENCES:
patent: 4363111 (1982-12-01), Heightley et al.
patent: 4366559 (1982-12-01), Misaizu et al.
patent: 4606010 (1986-08-01), Saito
1984 IEEE International Solid-State Circuits Conference, Feb. 24, 1984, pp. 278, 279.
Electronics, Jun. 14, 1984, AMR Mohsen et al., "C-MOS 256-K RAM", pp. 138-143.
1984 IEEE International Solid-State Circuits Conference, Feb. 22, 1984, pp. 104-105.

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