Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-04-12
2001-06-19
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S230030, C365S230080
Reexamination Certificate
active
06249483
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having a circuit for latching data on a data line of a data output path, and a related data latching method for the semiconductor memory device.
In the read operation of general semiconductor memory devices, e.g., synchronous DRAMs, row addresses and column addresses are specified to access a given memory cell. Column address transition is detected by a circuit that provides timing pulses for enabling a data output register after a predetermined delay time. The delay time is necessary for precharging, address decoding, and a sensing or driving operation, and results in it taking a long time to perform a read command. The data latched by the data output register is data of a memory cell selected from a memory cell array block.
A data output path includes sense-amplifiers positioned at the ends of a memory cell array for amplifying the data read from a memory cell. The data amplified by the sense-amplifiers is transmitted to the data output register through a data line. The data output register is positioned near input/output pads of a chip. Since the sense-amplifiers and the data output register are spaced apart from each other, a transmission delay is caused between the valid window of the data read from the memory cell and the time at which the data is latched by the data output register.
Newly read data must be latched after the data previously latched from the memory cell array is stored in the data output register. However, if the data is read later than the timing pulse that enables the data output register and is loaded on the data line with a transmission delay, then the read data may be lost. In other words, since the data output register cannot latch the data during the valid window of the previously read data, the previous data is lost.
The loss of the previous data causes malfunctions of synchronous DRAMs. Therefore, when latching the data on a data line of a data output path leading to the data output register of a synchronous DRAM, the data output register must latch the data without losing of previous data.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a semiconductor memory device having a circuit for latching data from a data line of a data output path.
It is another objective of the present invention to provide a method for latching data by a data output register of the semiconductor memory device.
Accordingly, to achieve the first objective, a synchronous semiconductor memory device is provided operating in synchronization with a clock signal, The synchronous semiconductor memory device comprises a memory cell block having a plurality of memory cells for outputting data from a selected memory cell to a data line, a data line control circuit for generating a data latch signal for releasing the latching of the data onto the data line in response to a first rising edge of the clock signal, synchronized with a read command, and latching the data on the data line in response to a second rising edge of the clock signal. The data latch signal is preferably activated within the valid window of the data from the selected memory cell.
A synchronous semiconductor memory device operating in synchronization with a clock signal is also provide that comprises a memory cell block having a plurality of memory cells for outputting data from a selected memory cell to a data line, sense amplifiers for sensing the data from the memory cells, a data output register for latching the data from the memory cells, data lines for connecting the sense amplifiers and the data output register for transmitting the sensed data to the data output register, and a data line control circuit for generating a data latch signal for releasing the latching of the data on the data line in response to a first rising edge of the clock signal, synchronized with a read command, and latching the data on the data line in response to a second rising edge of the clock signal.
The data line control circuit may itself comprise a first data line controller for generating a first data line control signal in response to a column select disable signal, a second data line controller for generating a second data line control signal in response to the clock signal and a column address, and a third data line controller activated by the second line control signal and deactivated by the first data line control signal, for generating the data latch signal having a predetermined time interval. The first data line control signal preferably operates to latch the data on the data line and disable the selection of a bit line of the memory cell, and the second data line control signal preferably operates to release the latching of the data on the data line and select a bit line of the memory cell.
The data line control circuit may also comprise a first data line controller for generating a first data line control signal in response to the clock signal and a column address, a second data line controller for generating a second data line control signal in response to the clock signal and the column address, and a third data line controller activated by the second line control signal and deactivated by the first data line control signal, for generating the data latch signal having a predetermined time interval. The first data line control signal preferably operates to latch the data on the data line, the column address is latched at the first falling edge of the clock signal and the first data line control signal is generated at the second rising edge of the clock, and the second data line control signal operates to release the latching of the data on the data line.
The data latch signal is preferably activated within the valid window of the memory cell data.
To achieve the second objective, a method is provided for latching data on a data line in a synchronous semiconductor memory device operating in synchronization with a clock signal, in which the data of a memory cell selected from a memory cell block having a plurality of memory cells is output to a data line. The method comprises generating the clock signal, activating a column select signal for selecting a bit line of the selected memory cell in accordance with a read command synchronized with the first rising edge of the clock signal, loading the bit line data of the selected memory cell on the data line in response to the column select signal, releasing latching of the data on the data line in response to the rising edge of the first clock, deactivating the column select signal in response to the second rising edge of the clock signal, and latching the data on the data line in response to the second rising edge of the clock signal.
According to the present invention, since a data latch signal is activated during the valid window of the data of the data line, the data of the data line of the data output path that leads to the data output register can be latched without a loss of data.
REFERENCES:
patent: 6172935 (2001-01-01), Wright et al.
Fears Terrell W.
Jones Volentine, L.L.C.
Samsung Electronics Co,. Ltd.
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