Semiconductor memory device having a boost circuit

Details Semiconductor memory device having a boost circuit Semiconductor memory device having a boost circuit

1991-08-19

1993-10-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including signal clamping

36523006, G11C 11407

Patent

active

052532046

ABSTRACT:
A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a word line selection circuit for selecting a word line, a bit line selection circuit for selecting a bit line, an input/output circuit for supplying data to be written to a selected memory cell via the selected bit line and for reading data from the selected memory cell via the selected bit line, a word line driver including a MOS transistor having a drain supplied with a supply voltage and a source connected to the word line selection circuit for supplying a word line voltage to the selected word line via the word line selection circuit, a word line boosting circuit connected to the drain of the MOS transistor for boosting the word line voltage via the MOS transistor, a boosting capacitor connected across the source and the gate of the MOS transistor, and a clamping circuit connected to the gate of said MOS transistor for clamping the voltage level at a predetermined level.

REFERENCES:
patent: 4807190 (1989-02-01), Ishii et al.
patent: 5051959 (1991-09-01), Nakano et al.
IEEE Journal of Solid-State Circuits, vol. 16, No. 5, Oct. 1981 pp. 492-498, Taniguchi et al. "Fully Boosted 64K Dynamic Ram with Automatic and Self Refresh".
Patent Abstracts of Japan, vol. 7, No. 152, Jul. 5, 1983, JP-A 58-62895.

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