Semiconductor memory device having a bit compressed test mode an

Details Semiconductor memory device having a bit compressed test mode an Semiconductor memory device having a bit compressed test mode an

1997-08-08

1999-01-26

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

G11C 700

Patent

active

058645101

ABSTRACT:
A semiconductor memory device is tested in a bit-compressed test mode wherein a plurality of banks of memory cells, which are disposed in association with respective I/O pins, are tested through one of the I/O pins. During the bit-compressed test mode, a check mode is additionally entered to examine whether the memory device actually stays in the bit-compressed test mode. The result of check by the check mode is supplied through the one of the I/Os pin delegating the plurality of I/O pins. The bit-compressed test mode is effected with accuracy.

REFERENCES:
patent: 5511029 (1996-04-01), Sawada et al.
patent: 5708601 (1998-01-01), McKenney et al.

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