Semiconductor memory device having a back-bias voltage generator

Details Semiconductor memory device having a back-bias voltage generator Semiconductor memory device having a back-bias voltage generator

1988-09-27

1990-10-16

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

3072962, G11C 702

Patent

active

049640828

ABSTRACT:
In typical MOS integrated circuit devices, the level of the back-bias voltage which is generated by a built-in back-bias generation circuit and is supplied to a semiconductor substrate is changed by an undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant. Instead, it becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, a back-bias voltage generation circuit is provided which has output capacity of a plurality of levels. Its output capacity is increased in response to an operation control signal of the main circuit. The level change of the back-bias voltage generation circuit can further be reduced by providing a level detection circuit for detecting the level change and a feedback circuit for controlling the back-bias voltage generation circuit in accordance with the output of the level detection circuit.

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patent: 4780854 (1988-10-01), Watanabe et al.

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