Semiconductor memory device generating accurate internal...

Details Semiconductor memory device generating accurate internal... Semiconductor memory device generating accurate internal...

2000-01-24

2001-06-12

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S230060, C365S189090

Reexamination Certificate

active

06246621

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device in which data values are sensed by current-to-voltage conversion, more particularly to the provision of a suitable reference current and reference voltage in this type of memory device.
2. Description of the Background Art
Current signals are used for data transport in, for example, non-volatile memory devices with single-transistor memory cells. When selected, the memory cells either conduct or block current, depending on the stored data value. Sensing circuits in the memory device convert the current flow to a data voltage signal Vs that has a high level or a low level, depending on the stored data value.
Such a memory device also has reference memory cells that always conduct current when selected. The sensing circuits convert a reference current received from the reference memory cells to a reference voltage signal Vref having a level intermediate between the high and low Vs levels. The difference between Vs and Vref is amplified to produce a ‘1’ or ‘0’ data output signal.
For quick and reliable amplification of the Vs-Vref difference, the reference voltage level Vref is preferably disposed halfway between the two Vs levels. In conventional memory devices, however, depending on the location of the memory cell being read, or on the data stored in other memory cells, the Vref level may be quite close to one of the two Vs levels. A resulting problem is that extra time must be allowed for amplification of the Vs-Vref difference, so the stored data cannot be accessed quickly. In the worst case, the wrong data value may be read.
Further explanation of this problem will be given in the detailed description of the invention.
SUMMARY OF THE INVENTION
A general object of the present invention is to shorten the read access time of a semiconductor memory device.
A more specific object is to provide a suitable reference current and reference voltage for use in reading data in a semiconductor memory device.
According to a first aspect of the invention, a semiconductor memory device has two types of transistors with different on-resistances. The transistors have control terminals coupled to a plurality of word lines. Transistors of the type with the higher on-resistance are switched on and off according to the word-line potential. Transistors of the other type remain switched on regardless of the word-line potential. The semiconductor memory device has at least one column of transistors of these types coupled in series, conducting a cell current when all switched on, each of the transistors constituting a memory cell.
The semiconductor memory device also has a reference amplifier receiving a reference current and generating a reference voltage, and a data sensing amplifier using the reference voltage to convert the cell current to a data voltage signal.
The reference current is supplied by a reference column having two parallel current paths joining at a common node, which is coupled to the reference amplifier. Each current path has substantially equal numbers of transistors of the above two types, coupled in series. Each word line is coupled to the control terminals of one transistor on each current path, these two transistors being of opposite type.
Reference current flows on one of the two parallel current paths at a time. A suitable reference current is obtained, because substantially equal numbers of transistors of the two types are present on the current path. A suitable reference voltage is therefore obtained.
According to a second aspect of the invention, a semiconductor memory device has a plurality of reference amplifiers converting respective reference currents to reference voltages, a plurality of data sensing amplifiers using the reference voltages to convert respective cell currents to data voltage signals, and a memory cell array supplying the reference currents and cell currents. At least two of the data sensing amplifiers receive cell currents from parts of the memory cell array having different layouts. Every interconnected data sensing amplifier and reference amplifier, however, receive a reference current and cell current from parts of the memory cell array having mutually identical layouts.
The identical layouts assure the supply of a suitable reference current to each reference amplifier and a suitable reference voltage to each data sensing amplifier.


REFERENCES:
patent: 5487045 (1996-01-01), Trodden
patent: 6075722 (2000-06-01), Hibino
patent: 6118706 (2000-09-01), Smayling et al.

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