Semiconductor memory device formed on semiconductor substrate

Details Semiconductor memory device formed on semiconductor substrate Semiconductor memory device formed on semiconductor substrate

2001-10-23

2002-11-19

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257S296000, C257S297000, C257S300000, C257S301000, C257S302000, C257S303000, C257S304000, C257S306000, C257S308000, C257S311000, C257S327000, C257S329000, C257S330000, C257S331000, C257S332000, C257S333000, C257S334000, C365S063000, C365S051000, C365S230030, C365S190000, C365S149000

Reexamination Certificate

active

06483139

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device formed on a semiconductor substrate.
2. Description of the Background Art
In recent years, as a result of the progress made in achieving in higher integration of a dynamic random access memory (hereinafter referred to as a DRAM), a capacitor of a memory cell is given a complex three-dimensional structure. In order to mount such a DRAM onto a system LSI, in addition to a usual CMOS logic process, a process step for forming a capacitor of a memory cell of the DRAM and a planarizing step for reducing a step between a peripheral circuit portion and the capacitor having the three-dimensional structure are required. Thus, when the DRAM is mounted on a system LSI, there was a problem of a significant increase in the number of the process steps which led to an increase in the chip cost.
On the other hand, a memory cell of a static random access memory (hereinafter referred to as an SRAM) does not include a capacitor so that it can be formed by the CMOS logic process alone. Thus, the above problem that occurs when mounting the DRAM onto the system LSI is solved if the SRAM is mounted onto the system LSI.
The SRAM, however, involves the following problems. In the DRAM, greater reduction in the size of a memory cell is being effected along with the progress in the microfabrication technology, and according to a 0.18 &mgr;m DRAM process, for instance, a memory cell of 0.3 &mgr;m
2
is realized. On the other hand, in the SRAM, a memory cell is formed by two P-channel MOS transistors and four N-channel MOS transistors and is subject to restrictions such as the distance requirement in separating a P-type well and an N-type well so that the reduction in the size of the memory cell has not progressed as much as it has in a DRAM even with the progress made in the microfabrication technology. For instance, an SRAM memory cell employing the 0.18 &mgr;m CMOS logic process is about 7 &mgr;m
2
, which is twenty times as large as or larger than a DRAM memory cell. Thus, increase in the memory capacity of the SRAM results in significant increase in the chip size so that it becomes extremely difficult to mount an SRAM whose memory capacity is 4 Mbits or greater onto the system LSI.
For these reasons, an SRAM has conventionally been used as a cache memory, a register file memory, or the like for a processor. Since the SRAM does not require the complex memory control involved in data refresh which is indispensable to a DRAM, the SRAM is also used as a main memory in portable electronic equipment and the like.
The features of the portable electronic equipment, however, are being significantly improved as such equipment now handles dynamic images so that a larger capacity memory is being required.
SUMMARY OF THE INVENTION
Thus, the main object of the present invention is to provide a large-capacity semiconductor memory device at a low cost.
A semiconductor memory device according to the present invention includes a memory cell having an MOS transistor and a capacitor connected in series for storing a data signal, wherein the MOS transistor includes a gate insulating film formed on a surface of a semiconductor substrate, a gate electrode formed on a surface of the gate insulating film, and an impurity diffusion region formed on the surface of the semiconductor substrate on either side of the gate electrode, the capacitor includes an impurity diffusion region formed on the surface of the semiconductor substrate, an insulating film formed on a surface of the impurity diffusion region, and a plate electrode formed on a surface of the insulating film for receiving a reference potential, and the gate electrode of the MOS transistor and the plate electrode of the capacitor are formed by the same interconnection layer. Thus, there is no need separately to provide interconnection layers for the electrode of the capacitor and for a storage node, and the semiconductor memory device can be produced by the CMOS logic process alone so that reduction in the chip cost can be achieved. In addition, the gate insulating film of the MOS transistor and the insulating film of the capacitor are made to have the same thickness so that the distance between the MOS transistor and the capacitor can be shortened, and the reduction in the chip size can be achieved. Moreover, a dynamic memory cell is employed so that the memory capacity can be increased when compared with the case where a static memory cell is employed.
Preferably, the semiconductor memory device is formed on the semiconductor substrate together with a logic circuit including an MOS transistor. A gate electrode of the MOS transistor of the logic circuit, the gate electrode of the MOS transistor of the memory cell, and the plate electrode of the capacitor are formed by the same interconnection layer. In this case, a system LSI including the semiconductor memory device and the logic circuit can be produced by the CMOS logic process alone.
More preferably, the MOS transistor of the memory cell is an N-channel MOS transistor, and the semiconductor memory device further includes a word line connected to a gate of the N-channel MOS transistor; first and second bit lines, one of which is connected to a source of the N-channel MOS transistor; a first P-channel MOS transistor connected between the first bit line and a first node; a second P-channel MOS transistor connected between the second bit line and a second node; and a write circuit for writing a data signal into the memory cell. The write circuit performs the steps of supplying a ground potential to gates of the first and second P-channel MOS transistors to render the first and second P-channel MOS transistors conductive, supplying a boosted potential that is higher than a power-supply potential to the word line to render the N-channel MOS transistor of the memory cell conductive, causing one of the first and second nodes to attain the power-supply potential while causing the other node to attain the ground potential according to an externally supplied write data signal, and supplying a negative potential that is lower than the ground potential to gates of the first and second P-channel MOS transistors while supplying the power-supply potential to the word line. In this case, data can be written into a memory cell without destroying the gate insulating film of the N-channel MOS transistor of the memory cell.
More preferably, an absolute value of a threshold voltage of each of the first and second P-channel MOS transistors is set to be substantially equal to a voltage of a difference between the boosted potential and the power-supply potential. In this case, the data signal can be sufficiently written into the memory cell while a voltage applied to the gate insulating film of the N-channel MOS transistor of the memory cell is limited to the power-supply voltage or to a lower voltage.
More preferably, two memory cells are provided, and one data signal is stored using two memory cells, two word lines are provided, gates of N-channel MOS transistors of the two memory cells are respectively connected to the two word lines, and sources of the N-channel MOS transistors of two memory cells are respectively connected to the first and second bit lines. In this case, the data signal can be more reliably written/read.
More preferably, two memory cells are provided, and one data signal is stored using two memory cells, gates of N-channel MOS transistors of the two memory cells are both connected to the word line, and sources of the N-channel MOS transistors of the two memory cells are respectively connected to the first and second bit lines. In this case, also, the data signal can be more reliably written/read.
More preferably, the MOS transistor of the memory cell is a P-channel MOS transistor, and the semiconductor memory device further includes a word line connected to a gate of the P-channel MOS transistor; first and second bit lines, one of which is connect

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