Semiconductor memory device for suppressing noises occurring on

Details Semiconductor memory device for suppressing noises occurring on Semiconductor memory device for suppressing noises occurring on

1994-02-22

1995-05-23

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Noise suppression

365 63, 365210, 365 51, G11C 700

Patent

active

054187508

ABSTRACT:
A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.

REFERENCES:
patent: 4903344 (1990-02-01), Inoue
patent: 5051954 (1991-09-01), Toda
patent: 5299157 (1994-03-01), Kimura
IEEE Journal of Solid State Circuits, "A Blocked Oriented RAM with Half Sized DRAM Cell & Quasi Folded Data Line Architecture", vol. 26, No. 11, K. Kimura, et al. Nov. 1991, pp. 1511-1518.

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