Semiconductor memory device for reducing power dissipation durin

Details Semiconductor memory device for reducing power dissipation durin Semiconductor memory device for reducing power dissipation durin

1988-08-08

1990-06-12

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365203, 365154, 36518906, G11C 700, G11C 800

Patent

active

049339052

ABSTRACT:
A semiconductor memory device includes a control circuit for disabling a bit-line load circuit coupled to a column of memory cells in a static RAM only when a write enable signal and a column select signal are applied to the column.

REFERENCES:
patent: 4195356 (1980-03-01), O'Connell et al.
patent: 4202045 (1980-05-01), Kung et al.
patent: 4730279 (1988-03-01), Ohtani
patent: 4760561 (1988-07-01), Yamamoto et al.
patent: 4802128 (1989-01-01), Watanabe et al.
patent: 4802129 (1989-01-01), Hoekstra et al.
patent: 4813022 (1989-03-01), Matsui et al.
"A 25 ns 64 K SRAM" by Ozawa et al., IEEE Int'l Solid State Circuits Conference, San Francisco, Feb. 22-24, 1984, vol. 27, Conf. 31, pp. 218-219, 342.
"A 256 K CMOS RAM with Variable-Impedance Loads" by Yamamoto et al., 1985 IEEE Int'l Solid-State Circuits Conf., Digest of Technical Papers, pp. 58-59.
"A 10 .mu.W Standby Power 256 K CMOS SRAM" by Kobayashi et al., 1985 IEEE Int'l Solid-State Circuits Conf., Digest of Technical Papers, pp. 60-61.

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