Semiconductor memory device for reducing operating power consump

Static information storage and retrieval – Systems using particular element – Capacitors

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365205, 36518911, 36518909, G11C 1124

Patent

active

056468806

ABSTRACT:
A semiconductor memory device comprising a memory cell array connected to true and complementary bit lines, the memory cell array including a plurality of memory cells, a bit line sense amplifier for sensing and amplifying a small voltage difference between the true and complementary bit lines, a control signal generator for generating first and second control signals, a first pull-up driver for applying an external supply voltage to the bit line sense amplifier in response to the first control signal from the control signal generator, a second pull-up driver for applying an internal supply voltage to the bit line sense amplifier in response to the second control signal from the control signal generator, a pull-down driver for discharging a voltage from the bit line sense amplifier, a bit line precharge circuit for precharging the true and complementary bit lines, a switching circuit for transferring data on the true and complementary bit lines to true and complementary data bus lines in response to an output signal from a column decoder, respectively, and an internal supply voltage generator for generating the internal supply voltage and applying the generated internal supply voltage to the second pull-up driver.

REFERENCES:
patent: 5373477 (1994-12-01), Sigibayashi
patent: 5446694 (1995-08-01), Tanaka et al.

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