Semiconductor memory device for reducing number of input...

Details Semiconductor memory device for reducing number of input... Semiconductor memory device for reducing number of input...

2002-01-17

2003-11-11

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S230080

Reexamination Certificate

active

06646935

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the testing of semiconductor memory devices, and more specifically to a semiconductor memory device and method for reducing a number of input cycles needed to input a test pattern, and thereby shortens the testing time and also simplifies the test pattern.
2. Description of the Related Art
Semiconductor memory devices are tested to ensure that they operate properly. To test memory devices, a test pattern including a command and an address, as well as test data, should be provided therewith. When a serial access memory is tested, the command and the address must be serially inputted over a plurality of input cycles.
FIG. 1
shows a block diagram of a typical conventional serial access memory device. The memory device includes an I/O buffer
102
, a command register control circuit
103
, an address register control circuit
104
, a register control clock generator
105
, an address increment clock generator
106
, command registers
107
1
-
107
N
, a command decoder
108
, address registers
109
1
-
109
M+L
, counters
110
1
-
110
M
, an address decoder
112
, and a memory cell array
113
. The memory cell array
113
includes a plurality of memory cells arranged in rows and columns.
The I/O buffer
102
receives external I/O signals I/O
0
-I/O
P−1
developed by an external circuit (not shown). The I/O signals I/O
0
-I/O
P−1
sequentially transfer a test pattern including a command and an initial address.
The command is represented by N command values, and the initial address is represented by (M+L) initial address values, where N, M, and L are an integer. The N, M, and L are determined on the basis of the scale of the memory device.
Each of the N command values and the (M+L) initial address values are constituted by P bits, each of which is respectively associated with I/O signals I/O
0
-I/O
P−1
. Hereinafter, each of the N command values is respectively denoted by command values CM
1
-CM
N
, and each of the (M+L) initial address values is respectively denoted by initial address values AR
1
-AR
M+L
. The command values CM
1
-CM
N
are respectively outputted to the command registers
107
1
-
107
N
, and the initial address values AR
1
-AR
M+L
are respectively outputted to the address registers
109
1
-
109
M+L
.
The command register control circuit
103
sequentially activates the command register
107
1
-
107
N
in response to a register control signal
103
a
provided by an external circuit (not shown). The activation of each of the command register
107
1
-
107
N
is respectively synchronized with the inputs of the command values CM
1
-CM
N
.
The address register control circuit
104
sequentially activates the address registers
109
1
-
109
M+L
in response to a register control signal
104
a
provided by an external circuit (not shown). The activation of each of the address registers
109
1
-
109
M+L
is respectively synchronized with the inputs of the initial address values AR
1
-AR
M+L
.
The register control clock generator
105
is responsive to an external clock signal
105
a
for developing a register control clock signal
105
b
. The register control clock signal
105
b
is outputted to the command registers
107
1
-
107
N
and the address registers
109
1
-
109
M+L
.
The address increment clock generator
106
is responsive to another external clock signal
106
a
for developing an address increment clock signal
106
b
. The address increment clock signal
106
is outputted to the counters
110
1
-
110
M
.
The command registers
107
1
-
107
N
are sequentially activated by the command register control signal
103
b
to respectively latch the command values CM
1
-CM
N
. The latching of the command values is executed in synchronization with the register control clock signal
105
b
. The command registers
107
1
-
107
N
respectively outputs the latched command values CM
1
-CM
N
to the command decoder
108
.
The command decoder
108
decodes the command values CM
1
-CM
N
to generate a command that determines an access mode of an access to the memory cell array
112
. The command decoder
108
informs the counter
110
1
-
110
M
of the generated command.
The address registers
109
1
-
109
M+L
are sequentially activated by the address register control signal
104
b
to respectively latch the initial address values AR
1
-AR
M+L
. The latching of the initial address values AR
1
-AR
M+L
is executed in synchronization with the register control clock signal
105
b
. The address registers
109
1
-
109
M
respectively output the initial address values AR
1
-AR
M+L
to the counter
110
1
-
110
M
, while the remaining address registers
109
M+1-109
M+L
respectively output the initial address values AR
M+1
-AR
M+L
to the address decoder
112
. The initial address values AR
1
-AR
M
is representative of a lower address of the initial address, while the initial address values AR
M+1
-AR
M+L
are representative of an upper address of the initial address. In a serial access of the memory cell array
113
, the upper address of the accessed memory cells is fixed to the initial upper address represented by the initial address values AR
M+1
-AR
M+L
. Therefore, the initial address values AR
M+1
-AR
M+L
may be denoted by address values AAR
M+1
-AAR
M+L
which are representative of an upper address of the accessed memory cells in the following.
The counters
110
1
-
110
M
respectively generate address values AAR
1
-AAR
M
which are representative of a lower address of the memory cell to be accessed in the memory cell array
112
. The counters
110
1
-
110
M
respectively receive the initial address values AR
1
-AR
M
from the address register
109
1
-
109
M
to initialize the address values AAR
1
-AAR
M
respectively to the initial address values AR
1
-AR
M
before a serial access to the memory cell array
112
is started. During the serial access, the counters
110
1
-
110
M
respectively increment the address values AAR
1
-AAR
M
, and thereby increment the lower address of the accessed memory cell. The counters
110
1
-
110
M
also controls the address values AAR
1
-AAR
M
in responsive to the command determined by the command decoder
108
. The counters
110
1
-
110
M
output the address values AAR
1
-AAR
M
.
The address decoder
112
receives the address values AAR
1
-AAR
M
from the counter
110
1
-
110
M
and the address values AAR
M+1
-AAR
M+L
(which are respectively same as the initial address values AR
M+1
-AR
M+L
) from the address registers
109
M+1
-
109
M+L
. The address decoder
112
decodes the address values AAR
1
-AAR
M+L
to allow one of the memory cells in the memory cell array
113
to be accessed.
FIG. 2
is a timing chart showing the operation of a conventional serial access memory device. At first, the command register control signal
103
a
is activated for a period from a time S to a time T. The command register control circuit
103
, in response to the command register control signal
103
a
, sequentially activates the command registers
107
1
-&ohgr;
N
, while the command values CM
1
-CM
N
are sequentially inputted to the I/O buffer
102
. The command registers
107
1
-
107
N
respectively latch the command values CM
1
-CM
N
in synchronization with the register control clock signal
105
b
. The command decoder
108
, in response to the command values CM
1
-CM
N
, outputs a command that determines an operating mode. The serial input of the command values CM
1
-CM
N
requires N input cycles of the register control clock signal
105
b.
Then, the address register control signal
104
a
is activated for a period from time T to time V. The address register control circuit
104
, in response to the address register control signal
104
a
, sequentially activates the address registers
109
1
-
109
M+L
, while the initial values AR
1
-AR
M+1
are sequentially inputted to the I/O b

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