Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-11-13
2004-10-19
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S236000, C365S239000, C365S230060, C365S230030, C365S230090
Reexamination Certificate
active
06807121
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory), and more particularly to a refresh control method for controlling the refresh operation in a semiconductor memory device that includes a memory cell array that is constituted by a plurality of mats equipped with normal word lines and redundant word lines.
2. Description of the Related Art
DRAMs store data by accumulating a charge in capacitors and therefore require refresh operations to be performed at a fixed cycle due to the leakage of the capacitor charge over the passage of time. These refresh operations are performed by successively activating word lines, reading the data of module cells that are connected to the activated word lines, amplifying the difference in potential by means of a sense amplifier, and rewriting to the original memory cells.
For example, refreshing a 64-kbits memory cell by means of a refresh command necessitates the input of 4000 (=256 Mbits/64 kbits) refresh commands to refresh all of the memory cells of a 256-Mbits semiconductor memory device. If refresh commands are applied at intervals of 7.8 &mgr;s, the time required to refresh all memory cells (hereinbelow referred to as the “refresh cycle”) 7.8 &mgr;s×4 k=32 ms. If the storage capacity in such a semiconductor memory device is increased to, for example, 512 Mbits, 8K refresh operations, i.e., 64 ms, is required to refresh all memory cells.
Due to the increase in storage capacity of semiconductor memory devices in recent years, however, designs for miniaturization of patterns have resulted in a decrease in the capacitance of capacitors for storing data. In addition, designs in which the operating voltage is lowered in order to increase operating speed have resulted in a lowering of the voltage that is applied to capacitors. Also, since the amount of charge that is stored in capacitors is determined as the product of the capacitance of the capacitors and the applied voltage, recent years have seen a downward trend in the amount of charge that is accumulated in capacitors in semiconductor memory devices. Failure to carry out the refresh operation before the disappearance of the charge that is stored in capacitors results in the destruction of the data that are held, and it has therefore been necessary in recent years to shorten the refresh cycle in semiconductor memory devices. Thus, when the storage capacity is increased from 256 Mbits to 512 Mbits, the refresh cycle must be kept the same as for the 256-Mbit storage capacity.
When the refresh operation is carried out in 32 ms for all memory cells of 512 Mbits, the above-described object can be achieved by changing the interval for inputting refresh commands from 7.8 &mgr;s to 3.9 &mgr;s, or to one-half the original interval. In actual DRAM control, however, processing for data reading and writing is also performed in addition to the refresh operation, and an increase in processing for refresh operations therefore causes the speed of data reading and writing to fall, and the interval for performing processing for refresh operations therefore cannot be made shorter than 7.8 &mgr;s.
To satisfy all of these conditions, the refresh operation for all memory cells of 512 Mbits must be carried out at a refresh cycle of 32 ms with the interval for the input of refresh commands kept at 7.8 &mgr;s.
Here, an external 8K Ref/internal 4K Ref standard has been adopted in the DDR (Double Data Rate) II mode that has been investigated by JEDEC (Joint Electron Device Engineering Council). As shown in
FIG. 1
a
, this external 8K Ref/internal 4K Ref standard is a standard in which, if all memory cells (512 Mbits) are refreshed by executing 8K (8192) refresh commands in 64 ms in the prior art, all memory cells (512 Mbits) are refreshed in 32 ms by refresh commands that are applied from the outside at the same cycle as in the prior art, i.e., by the input of 4K refresh commands.
Two methods can be considered when putting this external 8K Ref/internal 4K Ref standard into practice: a method as shown in
FIG. 1
b
in which the refresh operation is carried out for twice as many word lines as the prior art by one refresh command; and a method as shown in
FIG. 1
c
in which two refresh operations are performed serially within a chip by a single refresh command.
However, in a typical semiconductor memory device, redundant memory cells are supplied to provide a remedy for defective cells. Replacing word lines that contain defective memory cells with redundant word lines can save the entire semiconductor memory device from being rendered defective. However, these redundant word lines raise problems when the methods shown in
FIGS. 1
b
and
1
c
are used.
The following explanation regards a case in which one memory cell array is constituted by 16 mats, each mat being made up by 512 word lines and 8 redundant word lines.
FIG. 2
shows the memory cell array of a semiconductor memory device of this configuration. The memory cell array shown in this
FIG. 2
is made up of 16 mats
10
0
-
10
15
, each of mats
10
0
-
10
15
being made up of 512 word lines and 8 redundant word lines, and each of mats
10
0
-
10
15
being provided with a respective sense amplifier
9
0
-
9
15
. Redundant word lines are provided in a dispersed arrangement on each mat rather than in a concentrated arrangement because the failure of memory cells generally does not occur randomly but tends to occur in groups, resulting from, for example, the admixture of impurities in the process of fabricating the semiconductor memory device.
In a semiconductor memory device of this configuration, 64 bits of memory cells are refreshed by the selection of one word line. As a result, activating (512+8)×16=8320 word lines one at a time enables refreshing of all memory cells.
In contrast to the semiconductor memory device of this configuration, the external 8K Ref/internal 4K Ref standard can be realized if, when attempting to refresh 128 bits, i.e., twice the number of memory cells as in the prior art, by one refresh command, two word lines are activated and refreshed by the input of one refresh command as described in the foregoing explanation and as shown in
FIG. 1
b
. In a semiconductor memory device that contains the memory cell array shown in
FIG. 2
, however, each of mats
10
0
-
10
15
share sense amplifiers
9
0
-
9
16
, and when two word lines are simultaneously activated in the same mat, the stored data are destroyed.
In this type of semiconductor memory device, moreover, the replacement of any redundant word line and any normal word line in the same memory cell array is enabled in order to raise the replacement efficiency. For example, the configuration allows a word line of mat
10
1
to be replaced by a redundant word line of mat
10
15
. When such replacement of defective word lines and redundant lines that exceeds the range of one mat is performed, the activation of a normal word line within a particular mat is in actuality the activation of a redundant word line in a different mat. As a result, even though two word lines that belong to different mats are to be selected and activated to carry out a refresh operation, in some cases, two word lines in the same mat may be activated.
For example, as shown in
FIG. 3
, we consider a case in which, in order to simultaneously activate and refresh two word lines through the input of one refresh command, a method is employed of successively activating normal word lines having row addresses that are shifted by
4096
, i.e., normal word line
0
and normal word line
4096
, normal word line
1
and normal word line
4097
, and so on. In such a case, word line
0
belonging to mat
10
0
is replaced by redundant word line R
64
belonging to mat
10
8
, and word line
8191
belonging to mat
10
15
is replaced by redundant word line R
63
belonging to mat
10
7
. In this case, the intended simultaneous activation of normal word line
0
and normal word line
4096
act
Fujisawa Hiroki
Natsui Shun
Elpida Memory Inc.
Hayes & Soloway P.C.
Nguyen Viet Q.
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