Semiconductor memory device for providing margin of data...

Details Semiconductor memory device for providing margin of data... Semiconductor memory device for providing margin of data...

2001-08-06

2003-06-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189020, C365S230020

Reexamination Certificate

active

06577554

ABSTRACT:

The present application claims priority under 35 U.S.C. §119 to Korean Application No. 2000-45891 filed on Aug. 8, 2000, which is hereby incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for providing a margin of data setup time and data hold time of a data terminal DQ.
2. Description of the Related Art
Most recently, as high integration technology of semiconductor memory devices progresses, high-speed and high performance semiconductor memory devices can be provided. Synchronous dynamic random access memories (SDRAMs) typically run at operating frequencies ranging from 100-200 MHz and are synchronized with a clock signal to input data to a memory cell, or output memory cell data to a valid data window. In a computer system or an electric system running at higher speeds, a dual data rate DRAM (DDR DRAM) or a Rambus DRAM (RDRAM) support operating frequencies of about 500 MHz-1.6 GHz. In particular, in the case of RDRAM implementing a high speed operation having data transfer speeds of 800 Mbps, it is important to output data in synchronization with an external clock signal.
FIG. 1
shows a portion of a conventional RDRAM including blocks which synchronize data output with an external clock signal. Referring to
FIG. 1
, a RDRAM
100
includes a delay locked loop (DLL)
110
, an output replica
120
, a current controller
130
, an output multiplexer
140
, and an output driver
150
. The DLL
110
has input thereto an external clock signal EXTCLK and a feedback clock signal TCLKFB, and generates an internal clock signal TCLK and an internal delay clock signal TCLK
90
having phase delayed by 90 degrees with respect to the internal clock signal TCLK. The internal clock signal TCLK is used as a reference signal during operation of internal circuit blocks of the RDRAM
100
.
The output replica
120
replicates the internal delay clock signal TCLK
90
to generate a feedback clock signal TCLKFB. The DLL
110
compares a phase of the feedback clock signal TCLKFB with a phase of the external clock signal EXTCLK to generate the internal clock signal TCLK synchronized with the external clock signal EXTCLK. The output multiplexer
140
, which is one of internal circuit blocks in the RDRAM
100
, selects memory cell data in synchronization with the internal clock signal TCLK and transmits the selected memory cell data to the output driver
150
.
Referring to
FIG. 2
, the output multiplexer
140
receives the internal clock signal TCLK and separates internal clock signal TCLK to provide a clock signal CLK via inverters
12
and
14
, and to provide an inverted clock signal CLKB via inverters
16
,
18
, and
20
. A transmission gate
22
transmits memory cell data to the output driver (
150
of
FIG. 1
) via inverters
24
,
26
and
28
, in response to the clock signal CLK and the inverted clock signal CLKB.
Turning to
FIG. 1
, the current controller
130
supplies stable current to a bus line driven by a current mode output driver, and generates current control signals ICTRL<0:i> so as to make current changes due to variations in temperature, process, and power supply smaller. A representative current controller is disclosed in U. S. Pat. No. 5,254,883. The output driver
150
determines the voltage level of a data terminal DQ in response to the memory cell data selected by the output multiplexer and the current control signals ICTRL<0:i>. Furthermore, as the number of activated current control signals ICTRL<0:i> increases, the data transition time of the data terminal DQ becomes shorter.
Output data of the data terminal DQ in the RDRAM
100
is generally set to have a data setup time and a data hold time relative to an external clock signal EXTCLK. This is because the external clock signal EXTCLK works as a main clock signal for regulating the operation of the entire system (not shown), and the output data of the RDRAM
100
must therefore meet the data setup time and the data hold time specifications for the external clock signal EXTCLK. However, if the number of first NMOS transistors Ni in the output driver
150
which are selectively turned on by current control signals ICTRL<0:i> increases, output data of the data terminal DQ is transited at higher speeds. Thus, the data setup time and the data hold time set for the external clock signal EXTCLK are not satisfied. This causes malfunction of the entire system.
SUMMARY OF THE INVENTION
The present invention is therefore directed to providing a semiconductor memory device for securing a margin of data setup time and data hold time of a clock signal from a data terminal, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
Accordingly, to achieve the above objectives and others, the present invention provides a semiconductor memory device including an output multiplexer that delays the memory cell data by a predetermined time in response to current control signals for regulating current of a data terminal and that outputs delayed memory cell data; and an output driver that is driven by current control signals and the memory cell data to determine a voltage level of the data terminal.
The present invention also provides a semiconductor memory device including: a delay locked loop that receives an external clock signal and a feedback clock signal, compares a phase of the external clock signal with a phase of the feedback clock signal, and generates an internal clock signal and an internal delay clock signal; an output replica that delays the internal delay clock signal by a predetermined phase to generate the feedback clock signal; an output multiplexer that delays the memory cell data by a time and that outputs the delayed memory cell data in synchronization with the internal clock signal and responsive to current control signals for regulating current of the data terminal; and an output driver that is driven by the current control signals and the delayed memory cell data, to determine voltage level of the data terminal.
The present invention also provides a semiconductor memory device including and an output multiplexer that controls phase of the internal clock signal responsive to current control signals for regulating current of the data terminal and that outputs the memory cell data based on the controlled internal clock signal; and an output driver that is driven by the current control signals and the memory cell data to determine voltage level of the data terminal.
The present invention also provides a semiconductor memory device including: a delay locked loop that receives the external clock signal and a feedback clock signal, compares a phase of an external clock signal with a phase of the feedback clock signal, and generates the internal clock signal and an internal delay clock signal; an output replica that generates the feedback clock signal and controls a load of a line of the feedback clock signal responsive to the current control signals and the memory cell data; an output multiplexer that outputs the memory cell data in synchronization with the internal clock signal; and an output driver that is driven by the current control signals and the memory cell data to determine voltage level of the data terminal.
The present invention also provides a semiconductor memory device including: a delay locked loop that receives an external clock signal and a feedback clock signal, compares a phase of the external clock signal with a phase of the feedback clock signal, and generates an internal clock signal and an internal delay clock signal; an output replica that generates the feedback clock signal and controls a load of a line of the clock signal, responsive to current control signals for controlling current of the data terminal and the memory cell data; an output multiplexer that delays the memory cell data by a time in synchronization with the internal clock sig

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