Semiconductor memory device for preventing a late write from...

Details Semiconductor memory device for preventing a late write from... Semiconductor memory device for preventing a late write from...

2006-08-08

2006-08-08

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S222000, C711S151000, C711S152000, C711S158000, C710S244000

Reexamination Certificate

active

07089351

ABSTRACT:
A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

REFERENCES:
patent: 6735140 (2004-05-01), Fiscus et al.
patent: 6930945 (2005-08-01), Takahashi
patent: 2001/0017787 (2001-08-01), Hitoshi
patent: 1 050 882 (2000-11-01), None
patent: 2001-28190 (2001-01-01), None
patent: 2001-243764 (2001-09-01), None

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