Semiconductor memory device for operating in synchronization...

Details Semiconductor memory device for operating in synchronization... Semiconductor memory device for operating in synchronization...

2002-02-13

2003-01-21

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189011, C365S189050

Reexamination Certificate

active

06510095

ABSTRACT:

BACKGROUND OF
7
HE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device of a clock synchronous type and, more particularly, to a technology of reducing power consumption of a system on which the semiconductor memory device is mounted.
2. Description of the Related Art
An SDRAM (Synchronous DRAM) is generally known as the semiconductor memory device of the clock synchronous type. As the SDRAM, there are an SDR (Single Data Rate) type and a DDR (Double Data Rate) type. The SDR-SDRAM accepts a command and an address in synchronization with rising edges of a clock signal CLK, and inputs/outputs data in synchronization with the rising edges of the clock signal CLK. The DDR-SDRAM accepts the command and the address in synchronization with the rising edges of the clock signal and inputs/outputs the data in synchronization with both of the rising edge and a falling edge of the clock signal CLK.
FIG. 1
shows the operation of the SDR-SDRAM. In this example, a read burst length is set as “4”. The read burst length is the number of outputting read data successively, in response to one read command RD.
First, an active command ACT is supplied to a bank BK
0
in synchronization with the first clock signal CLK, and the bank BK
0
is activated (FIG.
1
(
a
)). Next, the active command ACT is supplied to a bank BK
1
in synchronization with the second clock signal CLK, and the bank BK
1
is activated (FIG.
1
(
b
)).
The read command RD is supplied to the bank BK
0
in synchronization with the third clock signal CLK. Data D
0
to D
3
which are read in the bank BK
0
are sequentially latched by a data latch in synchronization with rising edges of an internal clock signal ICLK (FIG.
1
(
c
)). The read data D
0
to D
3
which are latched by the data latch are outputted sequentially from a data input/output terminal DQ in synchronization with the next rising edges of the internal clock signal lCLK, respectively (FIG.
1
(
d
)).
Next, the read command RD is supplied to the bank BK
1
in synchronization with the eighth clock signal CLK. Data D
4
to D
7
which are read in the bank BK
1
are sequentially latched by the data latch in synchronization with rising edges of the internal clock signal
1
CLK (FIG.
1
(
e
)). The read data which are latched by the data latch are outputted sequentially from the data input/output terminal DQ in synchronization with the next rising edges of the internal clock signal
1
CLK, respectively (FIG.
1
(
f
)).
The read command RD is supplied again to the bank BK
0
in synchronization with the twelfth clock signal CLK, and, similarly to the above, the bank BK
0
is operated and read data D
8
to D
11
are sequentially outputted from the data input/output terminal DQ in synchronization with the rising edges of the internal clock signal ICLK (FIG.
1
(
g
)).
FIG. 2
shows the operation of the DDR-SDRAM. In this example, the read burst length is set as “8”. Incidentally, the DDR-SDRAM receives clock signals CLK and /CLK which are complementary to each other.
First, an active command ACT is supplied to a bank BK
0
in synchronization with the first clock signal CLK, and the bank BK
0
is activated (FIG.
2
(
a
)). Next, the active command ACT is supplied to a bank BK
1
in synchronization with the second clock signal CLK, and the bank BK
1
is activated (FIG.
2
(
b
)).
A read command RD is supplied to the bank BK
0
in synchronization with the third clock signal CLK. Data D
0
to D
7
which are read in the bank BK
0
are outputted to a parallel/serial conversion circuit by two bits, in synchronization with rising edges of an internal clock signal
1
CLK (FIG.
2
(
c
)). The parallel/serial conversion circuit sequentially converts the parallel read data (D
0
and D
1
, for example) into serial data. Then, the serial read data D
0
to D
7
are outputted from a data input/output terminal DQ in synchronization with internal clock signals CLKEVEN and CLKODD which are complementary to each other, respectively (FIG.
2
(
d
)). Namely, in the DDR-SDRAM, the read data D
0
to D
7
are sequentially outputted in synchronization with both of the rising edges and the falling edges of the clock signal CLK.
Next, the read command RD is supplied to the bank BK
1
in synchronization with the eighth clock signal CLK. Data D
8
to D
15
which are read in the bank BK
1
are outputted to the parallel/serial conversion circuit by two bits, in synchronization with the internal clock signal lCLK (FIG.
2
(
e
)). The parallel/serial conversion circuit converts the parallel read data into the serial data. Then, the serial read data D
8
to D
15
are outputted from the data input/output terminal DQ, in synchronization with the internal clock signals CLKEVEN and CLKODD which are complementary to each other, respectively (FIG.
2
(
f
)).
The read command RD is supplied again to the bank BK
0
in synchronization with the twelfth clock signal CLK, and, similarly to the above, the bank BK
0
is operated and read data D
16
to D
23
are outputted from the data input/output terminal DQ in synchronization with the clock signal CLK (FIG.
2
(
g
)).
The above-described SDR-SDRAM and the DDR-SDRAM accept the command and the address in synchronization with the rising edges of the clock signal CLK at all times. Therefore, a control circuit and the banks BK
0
and BK
1
inside the SDRAM operate in synchronization with the rising edges of the clock signal CLK, and perform read operation. Further, an output of the first read data is started in synchronization with the rising edge of the clock signal CLK at all times. As to write operation, the command and the address are accepted in synchronization with the rising edges of the clock signal LCK, and reception of write data is started in synchronization with the rising edge of the clock signal CLK, similarly to the read operation.
Thus, according to the conventional SDR-SDRAM and DDR-SDRAM, the command and the address are inputted in synchronization with the rising edges of the clock signal CLK only, and the control circuit and the banks inside the SDRAM are operated at timings with reference to the rising edge of the clock signal CLK. Hence, there is no alternative but to increase a frequency of the clock signal CLK, in order to increase a reception rate of the command. However, when the frequency of the clock signal CLK is increased, the power consumption of a clock synchronization circuit of the system on which the SDRAM is mounted is increased.
Moreover, since an internal circuit of the SDRAM is operated at timing with reference to the rising edge of the clock signal CLK in the conventional art, the assumption is not made that the command and the address are accepted in synchronization with the falling edges of the clock signal CLK. Supposing that the command and the address are accepted in synchronization with the falling edges of the clock signal CLK, it is impossible to operate the internal circuit at the timing with reference to the falling edge of the clock signal CLK. Namely, there is no merit in accepting the command and the address in synchronization with the falling edges of the clock signal CLK.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce power consumption of a system on which a semiconductor memory device is mounted, without reducing the data input/output rate for the semiconductor memory device.
According to one of the aspects of the semiconductor memory device of the present invention, a command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A timing control circuit sets timing to start outputting read data and timing to start inputting write data by a data input/output circuit at either the rising edge or the falling edge of the clock signal, respectively, in response to the edge of the clock signal in receiving the command signal. The data input/output circuit starts an output of the read data and an input of the write data in synchronization with the edges (either the rising edge or the f

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