Semiconductor memory device for maintaining level of signal line

Details Semiconductor memory device for maintaining level of signal line Semiconductor memory device for maintaining level of signal line

1998-04-30

2000-08-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365226, 36523006, G11C 1300

Patent

active

RE0368423

ABSTRACT:
A memory array MA.sub.0 is divided into four sub memory arrays by sense amplifier strips. Word drivers belonging to each sub memory array are connected to a corresponding segment boosted signal line. A fuse is connected to each segment boosted signal line. By blowing out a fuse, the sub memory array corresponding to the blown out fuse is no longer used. The sub memory array that is no longer used is exchanged with a spare sub memory array of a spare memory array.

REFERENCES:
patent: 5408435 (1995-04-01), McClure
"Subthreshold--Current Reduction Circuits for Multi-Gigabit DRAM's" Takeshi et al, General Research Laboratory, Hitachi Ltd. Date Unknown.
"WP3.4: 265MB DRAM Technologies for File Applications" G. Kitsukawa et al, 1993 IEEE ISSC Conference, 1993.
"Drawing of NEC's 4M DRAM products (42400)" sold in the U.S. before Dec. 28, 1993.
"High-Speed, High-Reliability Circuit Design for Megabit DRAM", Gillingham et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 8, Aug. 1991, pp. 1171-1175.
"Circuit Techniques For a Wide Word I/O path 64 Meg DRAM", Komatsuzaki et al., 1991 Symposium on VLSI Circuits, Digest of Technical Papers, May 30-Jun. 1, 1991, pp. 133-134.

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