Semiconductor memory device for internally controlling...

Details Semiconductor memory device for internally controlling... Semiconductor memory device for internally controlling...

2008-02-27

2008-12-09

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C365S189050, C327S108000

Reexamination Certificate

active

07463053

ABSTRACT:
Provided is a semiconductor memory device that is capable of internally controlling a strength of an output driver. The semiconductor memory device includes: an OCD (off chip driver) control signal generator for decoding EMRS and addresses to generate a plurality of external strength control signals or an internal driving signal; a self control signal generator for detecting a level of a driving voltage to generate a plurality of internal strength control signals in response to the internal driving signal; a control signal generator for generating a strength control signal in response to the external strength control signals or the internal strength control signals; and a data output driver for outputting data, the strength of the data output driver being controlled according to the strength control signal.

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