Semiconductor memory device for increasing access speed thereof

Details Semiconductor memory device for increasing access speed thereof Semiconductor memory device for increasing access speed thereof

2002-02-11

2004-11-09

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S310000

Reexamination Certificate

active

06815752

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a semiconductor memory device such as a dynamic random access memory (DRAM). Especially, the present invention is related to a structure of the semiconductor memory device and a method of fabricating the same.
2. Description of the Related Art
A memory cell of a semiconductor memory device is often constituted by a capacitor and a MOS (Metal Oxide Semiconductor) transistor. Such a memory cell is called 1T-1C cell. A dynamic random access memory (DRAM) includes a memory cell array in which 1T-1C cells are arranged in rows and columns.
FIG. 1
shows 1T-1C memory cells included in a conventional semiconductor memory device. The conventional semiconductor memory device is provided with MOS transistors formed in a surface portion of a P-type silicon substrate
100
. The MOS transistors include gate oxide films
110
, gate electrodes
103
, N-type source regions
113
, N-type drain region
114
, LDD (lightly doped drain) regions
111
, and sidewalls
112
. The gate electrodes
103
function as word lines of the memory device. To reduce the contact resistance, a cobalt silicide technique is adapted to the memory device. Cobalt silicide layers
132
are formed in the surface portion of the source regions
113
, and another cobalt silicide layers
132
′ is formed in the surface portion of the drain region
114
. In addition, still another cobalt silicide layer
133
is formed in the surface portion of the gate electrodes
103
. MOS transistors are electrically isolated from other elements (not shown) by STI (shallow trench isolation) dielectrics
101
.
The MOS transistors and the STI dielectrics
101
are covered with a silicon nitride film
115
and an inter-level dielectric
116
. The silicon nitride film
115
and the inter-level dielectric
116
are penetrated by capacitor plugs
104
formed of heavily doped polysilicon.
The inter-level dielectric
116
is covered with an inter-level dielectric
122
. The inter-level dielectric
122
are provided with holes to accommodate the memory cell capacitors.
Each of the memory cell capacitors includes a bottom electrode
106
, a dielectric layer
107
, a titanium nitride layer
108
, and a polysilicon layer
109
. The bottom electrode
106
is formed of heavily doped polysilicon. The bottom electrode
106
is electrically connected to the source region
113
through the capacitor plug
104
. The dielectric layer
107
is formed of tantalum oxide on the bottom electrode
106
. The titanium nitride layer
108
and the polysilicon layer
109
functions as an upper electrode of the memory cell capacitor.
The inter-level dielectric
122
and the memory cell capacitors are covered with an inter-level dielectric
135
. A bit line
131
formed of titanium nitride is formed on the inter-level dielectric
135
.
A bit line contact plug
102
is formed through the inter-level dielectric
116
,
122
, and
135
to electrically connect the bit line
131
to the drain region
114
of the MOS transistors.
To access the memory cell, the bit line
131
is firstly set at a predetermined potential. Then, the gate electrode
103
is pulled up to activate the MOS transistor. The activation of the MOS transistor allows an exchange of charges between the bit line
131
and the memory cell capacitors through the bit line contact plugs
102
, the MOS transistors and the capacitor plug
104
, The exchange of the charges causes a change in the potential of the bit line
131
. The potential of the bit line
131
is detected to define the data stored in the memory cell.
In the conventional memory device, the capacitor plugs
104
, formed of doped polysilicon, increases the resistance between the bit line
131
and the bottom electrodes
106
of the memory cell capacitors. This decreases the access speed of the memory device. The resistance between the bit line
102
and the memory cell capacitors is desirably decreased.
In addition, the conventional memory device requires an etching technique to form a contact hole having a high aspect ratio. Before forming the bit line contact plug
102
, a contact hole having a high aspect ration is necessary to be formed from the surface of the inter-level dielectric
135
to the drain region
114
of the MOS transistors. The necessity of forming a high-aspect-ratio contact hole makes the fabricating process difficult.
Yamanaka et al. disclose another semiconductor memory device for improving reliability and reducing a size of memory cells thereof in PCT Gazette (WO 09/28795). The semiconductor memory includes a memory cell region and a logical circuit region. The memory cell region includes a first transistor, and the logical circuit region includes second and third transistors that operate complementarily. The first, second and third transistors are covered with a dielectric. An interconnection of metal is formed on the dielectric over the memory cell region and the logical circuit region. Electrical connection between the interconnection and the first, second, and third transistor is achieved by a contact including a conductor formed in a hole fabricated through the dielectric. Yamanaka et al. discloses that the conductor included in the contact is formed of titanium nitride or titanium tungsten.
Shen et al. disclose still another semiconductor memory device for facilitating the fabrication process of a memory cell in U.S. Pat. No. 6,136,660 and Japanese Laid Open Patent Application (JP-A 2000-114475) corresponding thereto. The memory cell includes a field effect transistor and a stacked capacitor. The stacked capacitor has one plate formed by a platinum layer over the side walls of a portion of a dielectric layer that overlies a conductive layer that makes contact to a conductive plug connected to the storage node of the cell. The capacitor dielectric overlies the sidewalls and top of the dielectric layer portion and the other plate of the capacitor is formed by a platinum layer over the capacitor dielectric.
Ohno discloses still another semiconductor memory device having a cylindrical MIM (Metal Insulator Metal) structured capacitor for reducing junction leak, capacitance loss and reaction between silicon and electrode material in Japanese Laid Open Patent Application (JP-A 2000-156479). The memory device is provided with a semiconductor substrate on which an active element is formed. The semiconductor substrate is covered with an interlayer insulation film. A contact hole is formed through the interlayer insulation film to reach the active element. A plug made of conductive material is formed in the contact hole. A barrier layer is formed on the interlayer insulation film for covering at least an upper portion of the plug. A cylindrical bottom electrode is formed on the plug. A dielectric is formed on the bottom electrode, and an upper electrode is formed on the dielectric.
Saitoh et al. disclose still another semiconductor memory device having a COB (capacitor over bit line) structure for preventing defects in the fabrication process in Japanese Laid Open Patent Application (JP-A-Heisei 11-214644). The semiconductor memory device is provided with a first insulating film formed of silicon oxide on a semiconductor substrate. An interconnection is formed on the first insulating film. The interconnection is covered with a second insulating film. A memory cell capacitor including a high-∈ dielectric is formed on the second insulating film. The interconnection includes a conductive layer in contact with the first insulating film, the conductive layer being formed of refractory metal other than titanium, or refractory metal nitride.
SUMMARY OF THE INVENTION
An object of the present invention is to increase an access speed of a semiconductor memory by reducing a resistance between a bit line and memory cell capacitors.
Another object of the present invention is to facilitate the fabrication process of a semiconductor memory by avoid forming a contact hole having a high aspect ratio.
Still another object of the present invention is to

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