Semiconductor memory device for effecting erasing operation...

Details Semiconductor memory device for effecting erasing operation... Semiconductor memory device for effecting erasing operation...

2000-03-21

2001-12-04

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S230060, C365S185110, C365S200000

Reexamination Certificate

active

06327180

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-077432, filed Mar. 23, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device using MOS transistors of stacked gate structures as memory cells and capable of rewriting/reading out data and more particularly to the technique for replacing a defective cell by a redundancy cell when the defect occurs in a semiconductor memory device for effecting the erasing operation in the block unit.
A memory cell of an EEPROM for electrically erasing/programming data is generally constructed by a MOS transistor (nonvolatile transistor) of stacked gate structure using two-layered polysilicon layers which are isolated from each other by an insulating film as shown in FIG.
1
. This type of memory cell is disclosed in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 27 No. 11 November 1992 pp. 1540-1545.
In the above memory cell, a floating gate
11
is formed of a first-level polysilicon layer and a control gate is formed of a second-level polysilicon layer. A source region
14
and drain region
15
are separately formed in a silicon substrate
13
which lies below the floating gate
11
and control gate
12
. An inter-level insulating film
16
is formed on the entire portion of the main surface of the substrate
13
and a contact hole
17
is formed in that portion of the inter-level insulating film
16
which lies on the drain region
15
. A data line (bit line)
18
formed of metal such as aluminum is formed on the inter-level insulating film
16
and in the contact hole
17
and electrically connected with the drain region
15
.
Next, the data programming, reading and erasing operations in the memory cell of the above structure is explained.
The programming operation is effected by, for example, respectively setting the drain potential VD, control gate potential VCG and source potential VS at 5.0V, 9.0V and 0V and injecting hot electrons into the floating gate
11
to change the threshold voltage.
The erasing operation is effected by, for example, setting the control gate potential VCG at −7.0V, setting the drain into the electrically floating state and setting the source potential VS at 5.0V, for example. In this state, electrons in the floating gate
11
are withdrawn into the source region
14
by the tunnel effect.
The reading operation is effected by, for example, respectively setting the control gate potential VCG, drain potential VD and source potential VS at 4.8V, 0.6V and 0V. At this time, if the memory cell is set in the programmed state, no current flows between the source and drain. Memory data at this time is set as “0”. If the memory cell is set in the erased state, a current of approx. 30 &mgr;A flows between the source and drain. Memory data at this time is set as “1”.
In the memory cell with the above structure, various defects will occur in the manufacturing process due to the lattice defect in the silicon substrate
13
and the defect of the insulating film. For example, it is considered that the silicon substrate
13
will be short-circuited to the floating gate
11
or control gate
12
. In this case, it becomes impossible to effect the correct programming, erasing and reading operations. This problem becomes more serious with an increase in the memory capacity of the semiconductor memory device, and particularly, it is important at the starting time of the manufacturing line for performing the fine patterning process.
In order to solve the above problem, various types of redundancy circuits are generally provided in the semiconductor memory device. The redundancy technology is disclosed in, for example, Japanese Patent Application KOKAI Publication No. 11-213691.
FIG. 2
is a block diagram showing the schematic construction of a nonvolatile semiconductor memory device using MOS transistors with the above stacked gate structures as memory cells and having redundancy cells which will be used instead of defective cells. The semiconductor memory device includes a column address buffer
20
, column decoder
21
, row address buffer
22
, R/D (redundancy) address storing section
23
, R/D address comparing section
24
, block address buffer
25
, block cores
26
-
0
to
26
-n, sense amplifier (S/A)
27
, input/output buffer
28
and input/output pad
29
. Each of the block cores
26
-
0
to
26
-n includes a memory cell array
30
, row decoder
31
, R/D memory cell array
32
, R/D row decoder
33
, block decoder
34
and column selection gates CT
0
to CTj.
In the memory cell array
30
, memory cells having the same structure as shown in
FIG. 1
are arranged in a matrix form. The drains of the memory cells on each column are commonly connected to a corresponding one of bit lines BL
0
to BLj and the control gates of the memory cells on each row are commonly connected to a corresponding one of word lines WL
0
to WLk.
A row address signal ADDRi is input from the exterior to the row address buffer
22
and an output signal ARSi thereof is supplied to the row decoders
31
of the block cores
26
-
0
to
26
-n as an internal row address signal. One of the word lines WL
0
to WLk is selected by the row decoder
31
. A column address signal ADDCi is input from the exterior to the column address buffer
20
. An output signal ACSi of the column address buffer
20
is supplied to and decoded by the column decoder
21
as an internal column address signal and then supplied to the column selection gates CT
0
to CTj of each of the block cores
26
-
0
to
26
-n. One of the bit lines BLO to BLj is selected by the column selection gates CT
0
to CTj and one memory cell connected to the selected bit line and selected word line is selected.
Stored data of the selected memory cell is supplied to the sense amplifier
27
via the selected column selection gate, amplified and then output to the exterior from the input/output pad
29
via the input/output buffer
28
.
Next, a case wherein a memory cell in the memory cell array
30
is defective is considered. In the R/D memory cell array
32
used for replacement of the defective cell, a plurality of memory cells are arranged in a matrix form like the memory cell array
30
. In the present device, addresses of the defective portions are previously stored in the R/D address storing section
23
. An output signal AFi of the R/D address storing section
23
is compared with an output signal ARSi of the row address buffer
22
in the R/D address comparing section
24
. If the result of comparison indicates coincidence of the output signals, a signal HITR is output from the R/D comparing section
24
and supplied to the R/D row decoders
33
of the block cores
26
-
0
to
26
-n. Then, one of the R/D row decoders
33
which corresponds to the memory cell array
30
containing the defective cell is set into the enable state to select one of word lines WLRD-
0
to WLRD-I. At this time, one of the row decoders
31
which corresponds to the memory cell array
30
containing the defective cell is forcedly set into the non-selected state by a signal ROWDIS output from the R/D address comparing section
24
. The sources of all of the memory cells in the memory cell array
30
and R/D memory cell array
32
are connected to a corresponding one of common source lines SLi (i=0 to n), an output signal of the block decoder
34
is commonly supplied thereto and the erase operation is simultaneously effected at the erasing time (block erasing).
Generally, a plurality of erasing cores (corresponding to the block cores
26
-
0
to
26
-n in
FIG. 2
) are present in one semiconductor memory device. Next, the erase operation of the present device is explained in detail. A source potential 5.0V is applied from the common source lines SLi (i=0 to n) to the source lines of the memory cells in the memory cell array
30
and R/D memory cell array
32
in each of the block cores
26
-
0

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