Semiconductor memory device for controlling output timing of...

Details Semiconductor memory device for controlling output timing of... Semiconductor memory device for controlling output timing of...

2006-04-11

2006-04-11

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S236000

Reexamination Certificate

active

07027336

ABSTRACT:
A semiconductor memory device is capable of controlling the data output timing depending on the operating frequency so as to output data with optimized for the operating frequency. Further, in the high frequency operation, the memory device can output data reliably so as to facilitate development of high frequency memory device. The semiconductor memory device comprises a frequency sensing unit for sensing an operating frequency by sensing an amount of lead of a delay locked clock in a delay locked loop compared to an external clock signal, an output enable controlling unit for outputting an output enable signal in response to a CAS latency with controlling the output timing of the output enable signal based on the frequency that is sensed by the frequency sensing unit, and a data output buffer for outputting data that is transferred from a memory core region in response to the output enable signal.

REFERENCES:
patent: 2003/0198097 (2003-10-01), Kono
patent: 2004/0008566 (2004-01-01), Song
patent: 2005/0108590 (2005-05-01), Janzen

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