Semiconductor memory device for adjusting impedance of data...

Details Semiconductor memory device for adjusting impedance of data... Semiconductor memory device for adjusting impedance of data...

2008-01-29

2008-01-29

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C327S308000, C365S189050

Reexamination Certificate

active

07323900

ABSTRACT:
A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the reference signal; an impedance measuring unit for measuring an impedance of the test pad based on the adjusted value to output the test signal; an impedance adjusting unit for adjusting an impedance of a data I/O pad to have an impedance value corresponding to the adjusted value outputted when the test signal is equal to the reference signal; an impedance control unit for controlling the comparing unit so that the adjusted value is outputted when the test signal is equal to the reference signal; and a reference signal control unit for adjusting a voltage level of the reference signal.

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